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[203.254.224.24]) by mx.google.com with ESMTP id g1si59497908paw.158.2013.01.07.05.03.06; Mon, 07 Jan 2013 05:03:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MG9003UGAX5M810@mailout1.samsung.com>; Mon, 07 Jan 2013 22:03:05 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id B2.70.01231.987CAE05; Mon, 07 Jan 2013 22:03:05 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-16-50eac7895807 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 32.70.01231.987CAE05; Mon, 07 Jan 2013 22:03:05 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MG900HHWAUUOH80@mmp2.samsung.com>; Mon, 07 Jan 2013 22:03:05 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, kmpark@infradead.org Subject: [PATCH 1/4 V2] EXYNOS: Add functions for power initialisation Date: Mon, 07 Jan 2013 18:38:43 +0530 Message-id: <1357564126-13275-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1357564126-13275-1-git-send-email-rajeshwari.s@samsung.com> References: <1357564126-13275-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRmVeSWpSXmKPExsWyRsSkTrfz+KsAg+MNIhYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgynjQuZyvYJVBxq/kKUwPjX94uRk4OCQETiatnbzNB 2GISF+6tZ+ti5OIQEljKKPHjwj7mLkYOsKIPyxIh4tMZJeYvOM8O4Uxkklh2ezcjSDebgJHE 1pPTwGwRAQmJX/1XwWxmgSKJqd2LWUFsYQE3idmHV7CA2CwCqhIPpp0A28wr4CHx/8cyFogr FCSOTf0KVs8p4CnR+X8WM4gtBFRz6Q/ELhYBAYlvkw+xQBwnK7HpADPIPRICt9kkLnVcYIOY IylxcMUNlgmMwgsYGVYxiqYWJBcUJ6XnGuoVJ+YWl+al6yXn525iBIbj6X/PpHYwrmywOMQo wMGoxMN70eBVgBBrYllxZe4hRgkOZiURXpsuoBBvSmJlVWpRfnxRaU5q8SFGH6BLJjJLiSbn A2MlryTe0NjE3NTY1NLIyMzUFIewkjgv46knAUIC6YklqdmpqQWpRTDjmDg4pRoYWx7oOex+ sbFt3ZSUNa9Lv/x+kRxx9dvlN5s739+c/P+G3/PZxVfl9f4t3PL7fadT2rPHQk09XX13dh2Y wRVkfjbR5cxKq03XlwmuXhkgfevNqRkvImVYj1euPzC9u/LR7g+TbB4EOR07oGl5MOh82v6c Z7061deZf/94kT6p1tfjiYjDB/a5n9cqsRRnJBpqMRcVJwIAxkr+U3QCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsVy+t9jQd3O468CDB7e57B4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmPGkcTlbwS6B ilvNV5gaGP/ydjFycEgImEh8WJbYxcgJZIpJXLi3nq2LkYtDSGA6o8T8BefZIZyJTBLLbu9m BKliEzCS2HpyGpgtIiAh8av/KpjNLFAkMbV7MSuILSzgJjH78AoWEJtFQFXiwbQTTCA2r4CH xP8fy1ggtilIHJv6FayeU8BTovP/LGYQWwio5tKf3YwTGHkXMDKsYhRNLUguKE5KzzXUK07M LS7NS9dLzs/dxAgO9mdSOxhXNlgcYhTgYFTi4b1o8CpAiDWxrLgy9xCjBAezkgivTRdQiDcl sbIqtSg/vqg0J7X4EKMP0FUTmaVEk/OBkZhXEm9obGJuamxqaWJhYmaJQ1hJnJfx1JMAIYH0 xJLU7NTUgtQimHFMHJxSDYyaWhXPwyZW+S/o3Ba78v3bW7ExBX2pJZ+vtf+vEfuubNYuPC3I QuSTrpRzstLL7T99tXb0MLYdPPf3jHhSRUy1jSp/S/BOg5mude1cDpXX172W0Hmympszbq5u uVGheJtK9nRHX+HpOiGS5vb1DpXZUxpN36zhXGZ06tyyRyuefF0q6H2YX4mlOCPRUIu5qDgR AMdkBgijAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkOC2M4RgJEiUplptmOkVyjE0fxvQdcHOXIV4DMxE7sjz60rTtQgsqfLLZLNWXDetF8Q0Ru This patch adds functions to intialsise power registers during spl boot. Signed-off-by: Rajeshwari Shinde --- Changes in V2: - Moved from second patch to first patch - Renamed ps_hold_setup to power_ps_hold_setup - Added explanation before each power function definition arch/arm/cpu/armv7/exynos/power.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 10 ++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index d4bce6d..f0c107c 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -95,3 +95,30 @@ void set_dp_phy_ctrl(unsigned int enable) if (cpu_is_exynos5()) exynos5_dp_phy_control(enable); } + +uint32_t power_read_reset_status(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + return power->inform1; +} + +void power_ps_hold_setup(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Set PS-Hold high */ + setbits_le32(&power->ps_hold_control, + EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); +} + +void power_exit_wakeup(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + typedef void (*resume_func)(void); + + ((resume_func)power->inform0)(); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index d2fdb59..f6d0278 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -864,4 +864,14 @@ void set_dp_phy_ctrl(unsigned int enable); #define EXYNOS_DP_PHY_ENABLE (1 << 0) +#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) + +/* Read inform1 to get the reset status */ +uint32_t power_read_reset_status(void); + +/*Set ps_hold data drving value high */ +void power_ps_hold_setup(void); + +/* Read the resume function and call it */ +void power_exit_wakeup(void); #endif