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[203.254.224.24]) by mx.google.com with ESMTP id zn8si49930618pbc.322.2013.01.04.01.12.18; Fri, 04 Jan 2013 01:12:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MG300AEHG7XGLC0@mailout1.samsung.com>; Fri, 04 Jan 2013 18:12:17 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.123]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 00.70.01231.1FC96E05; Fri, 04 Jan 2013 18:12:17 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-18-50e69cf136fb Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 8F.60.01231.0FC96E05; Fri, 04 Jan 2013 18:12:17 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MG30081AG7XXLA0@mmp1.samsung.com>; Fri, 04 Jan 2013 18:12:16 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH V4 8/9] SMDK5250: Enable EMMC booting Date: Fri, 04 Jan 2013 04:34:09 -0500 Message-id: <1357292050-12137-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> References: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkWvfjnGcBBkfWCFo8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKmHl+EWPBJNWKratfMzUw3pDrYuTkkBAwkVg8+z0L hC0mceHeerYuRi4OIYGljBKvnz5nhylatHADVGIRo8SdeftZIJxeJolNzXuZuxg5ONgEVCV+ LbYHaRARMJCY/mQ7K0iYWaBA4tluMZCwsICpxM6fm9hAbBag6uP/O8AW8wp4SOw7uZ4RYpec xIc9j9hBWjkFPCU2XREBMYWASq4eKoHoFJD4NvkQC0hYQkBWYtMBZpBbJARus0ncbX3FCjFF UuLgihssExiFFzAyrGIUTS1ILihOSs811CtOzC0uzUvXS87P3cQIDMTT/55J7WBc2WBxiFGA g1GJh9fyztMAIdbEsuLK3EOMEhzMSiK8n7WfBQjxpiRWVqUW5ccXleakFh9i9AG6ZCKzlGhy PjBK8kriDY1NzE2NTS2NjMxMTXEIK4nzMp56EiAkkJ5YkpqdmlqQWgQzjomDU6qBccmMUNUT t155vBT3zppmciDg/rr9vqo9m578XXLow6f9H/4G13y3vn+GlTvs2q2wL6pOJ/VLMvPVX+ZH 1e/b9q09+/yqeyZTPD8ELb5eFjfxhsCMJnmeeBmG8Hwlxqiqj3aPvaLzeW+ZVD12rlibdkj5 SpcFd/2t9pQJ1X89nueX7fSTPmyiosRSnJFoqMVcVJwIAKWH/kxxAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42I5/e+xgO7HOc8CDFY0slg8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzJh5fhFjwSTV iq2rXzM1MN6Q62Lk5JAQMJFYtHADG4QtJnHh3nogm4tDSGARo8SdeftZIJxeJolNzXuZuxg5 ONgEVCV+LbYHaRARMJCY/mQ7K0iYWaBA4tluMZCwsICpxM6fm8BmsgBVH//fwQJi8wp4SOw7 uZ4RYpecxIc9j9hBWjkFPCU2XREBMYWASq4eKpnAyLuAkWEVo2hqQXJBcVJ6rqFecWJucWle ul5yfu4mRnCYP5PawbiyweIQowAHoxIPr+WdpwFCrIllxZW5hxglOJiVRHg/az8LEOJNSays Si3Kjy8qzUktPsToA3TTRGYp0eR8YAzmlcQbGpuYmxqbWppYmJhZ4hBWEudlPPUkQEggPbEk NTs1tSC1CGYcEwenVAPjivB7Gw45nelRvC+o5pZwj//A476lC3RFjjFMjs4I26nw2dZG2kRr 8rYLRyey/TGNLJ6/9fDNPdwL1R9IslkEfvm3MKEhzn/2+YMB0787ndL1+1HumMLBZ62WKPBE kdfma/KZbtsFvIeXNS6Mf/hNhC8x2vzbzZhb6zZeyXl6p3j+Jo8tZnPklViKMxINtZiLihMB t0XAI6ACAAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQn+GyrMtuNxhYNzuLRqR/x8oqjkr1VCwvHYzfzw70M38OJVgBz6wbYVGgQ476RXt7g5ZKi3 This patch adds support for EMMC booting on SMDK5250. Changes from V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Changes from V3: No change. Signed-off-by: Amar --- board/samsung/smdk5250/clock_init.c | 15 +++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..154993c 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" @@ -664,3 +665,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..906e197 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,16 +23,38 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -40,23 +62,39 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = (void *) *(u32 *)irom_ptr_table[SPI_INDEX]; spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = (void *) *(u32 *)irom_ptr_table[MMC_INDEX]; copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_INDEX]; + end_bootop_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_END_INDEX]; + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + + break; + default: break; }