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[203.254.224.34]) by mx.google.com with ESMTP id e2si39400633paz.92.2012.12.31.02.36.30; Mon, 31 Dec 2012 02:36:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFW009QX5G7FY70@mailout4.samsung.com>; Mon, 31 Dec 2012 19:36:30 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id A8.C2.01231.DAA61E05; Mon, 31 Dec 2012 19:36:30 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-b4-50e16aad2e0c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 38.C2.01231.DAA61E05; Mon, 31 Dec 2012 19:36:29 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFW00JL05G0TP80@mmp1.samsung.com>; Mon, 31 Dec 2012 19:36:29 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH V3 8/9] SMDK5250: Enable EMMC booting Date: Mon, 31 Dec 2012 05:58:19 -0500 Message-id: <1356951500-22490-9-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> References: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsWyRsSkSndd1sMAg0lfWS0err/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBl3P21nbnglUrFzfVJDYwH5boYOTkkBEwk9j/ZywJh i0lcuLeerYuRi0NIYCmjxPoFl5lhiraf3gqVWMQo0b9yLTtIQkigl0ni/QGJLkYODjYBVYlf i+1BwiICBhLTn2xnBQkzCxRIPNstBmIKC5hKnD1SB1LBAlT8890pRhCbV8BD4sLta1AnyEl8 2PMIbDingKfE6S07mCEWeUjc7F7IDtErIPFt8iEWkJESArISmw4wgxwmIXCdTeLarOdQF0tK HFxxg2UCo/ACRoZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGIFhePrfM6kdjCsbLA4xCnAw KvHwcjE9DBBiTSwrrsw9xCjBwawkwvtWCyjEm5JYWZValB9fVJqTWnyI0QfokonMUqLJ+cAY ySuJNzQ2MTc1NrU0MjIzNcUhrCTO2+yREiAkkJ5YkpqdmlqQWgQzjomDU6qBsT49qrL+WNyl LefjqgJL3rDbKO5y5BOWO2enphQrIeC0+bjaxGX/N9f/zZrUJvyQa/cFpnUbDyYUVBWWJ2+Q D1Veei9S+bvgnpdHDipwzJ499fmPiw2Pq9tW3T+TqqrLp8aaw7hkzXc3z2p1ifMTL7TKfP68 dcFihyQ9niPW94LOe63bFuzjqsRSnJFoqMVcVJwIAAM5UI5wAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e+xgO7arIcBBpvOm1s8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzLj7aztzwSuV ipvrkxoYD8p1MXJySAiYSGw/vZUNwhaTuHBvPZDNxSEksIhRon/lWnaQhJBAL5PE+wMSXYwc HGwCqhK/FtuDhEUEDCSmP9nOChJmFiiQeLZbDMQUFjCVOHukDqSCBaj457tTjCA2r4CHxIXb 11ggNslJfNjzCGw4p4CnxOktO5ghFnlI3OxeyD6BkXcBI8MqRtHUguSC4qT0XEO94sTc4tK8 dL3k/NxNjOAgfya1g3Flg8UhRgEORiUeXi6mhwFCrIllxZW5hxglOJiVRHjfagGFeFMSK6tS i/Lji0pzUosPMfoAXTWRWUo0OR8YgXkl8YbGJuamxqaWJhYmZpY4hJXEeZs9UgKEBNITS1Kz U1MLUotgxjFxcEo1MBaKnjb9tfDVX46itC7Jh7duO2/wvS/gbadsqfzpv1zJ9wPhk3xXX7z2 +4ZYlf7naZZBX76v1nRv+W7kJlP0T6J9+vzm0J431SpXuqVZd22cx71ZfL+R95FfWrLBjA92 Pd6veWj5v8S8gMbZbbLR3K8vtXxPrvvoKchvHipl7WfforZolfL9ZiWW4oxEQy3mouJEAC99 7E+fAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlTh4Thfi/RXBmcoPradqTMaZQWwUpq16AuU6g0Xl04tSfJ2gG/ESkxJIm4YT0XBihCkBKC This patch adds support for EMMC booting on SMDK5250. Changes from V1: 1)Updated spl_boot.c file to maintain irom pointer table instead of using the #define values defined in header file. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Signed-off-by: Amar --- board/samsung/smdk5250/clock_init.c | 15 +++++++++++ board/samsung/smdk5250/clock_init.h | 5 ++++ board/samsung/smdk5250/spl_boot.c | 52 ++++++++++++++++++++++++++++++++----- 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..154993c 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "clock_init.h" #include "setup.h" @@ -664,3 +665,17 @@ void clock_init_dp_clock(void) /* We run DP at 267 Mhz */ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } + +/* + * Set clock divisor value for booting from EMMC. + * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz. + */ +void emmc_boot_clk_div_set(void) +{ + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; + unsigned int div_mmc; + + div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; + div_mmc |= FSYS1_MMC0_DIV_VAL; + writel(div_mmc, (unsigned int) &clk->div_fsys1); +} diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h index f751bcb..20a1d47 100644 --- a/board/samsung/smdk5250/clock_init.h +++ b/board/samsung/smdk5250/clock_init.h @@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void); * Initialize clock for the device */ void system_clock_init(void); + +/* + * Set clock divisor value for booting from EMMC. + */ +void emmc_boot_clk_div_set(void); #endif diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..906e197 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -23,16 +23,38 @@ #include #include +#include +#include +#include + +#include "clock_init.h" + +/* Index into irom ptr table */ +enum index { + MMC_INDEX, + EMMC44_INDEX, + EMMC44_END_INDEX, + SPI_INDEX, +}; + +/* IROM Function Pointers Table */ +u32 irom_ptr_table[] = { + [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */ + [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/ + [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer + -EMMC4.4 end boot operation */ + [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */ + }; + enum boot_mode { BOOT_MODE_MMC = 4, BOOT_MODE_SERIAL = 20, + BOOT_MODE_EMMC = 8, /* EMMC4.4 */ /* Boot based on Operating Mode pin settings */ BOOT_MODE_OM = 32, BOOT_MODE_USB, /* Boot using USB download */ }; - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -40,23 +62,39 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; - u32 (*copy_bl2)(u32, u32, u32); - + u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst); + u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); + void (*end_bootop_from_emmc)(void); + /* read Operation Mode ststus register to find the bootmode */ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; + spi_copy = (void *) *(u32 *)irom_ptr_table[SPI_INDEX]; spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: - copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + copy_bl2 = (void *) *(u32 *)irom_ptr_table[MMC_INDEX]; copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_EMMC: + /* Set the FSYS1 clock divisor value for EMMC boot */ + emmc_boot_clk_div_set(); + + copy_bl2_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_INDEX]; + end_bootop_from_emmc = + (void *) *(u32 *)irom_ptr_table[EMMC44_END_INDEX]; + + copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); + end_bootop_from_emmc(); + + break; + default: break; }