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[203.254.224.34]) by mx.google.com with ESMTP id d7si39389677paw.153.2012.12.31.02.36.26; Mon, 31 Dec 2012 02:36:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFW009QX5G7FY70@mailout4.samsung.com>; Mon, 31 Dec 2012 19:36:25 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C5.C2.01231.9AA61E05; Mon, 31 Dec 2012 19:36:25 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-9f-50e16aa91480 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 35.C2.01231.9AA61E05; Mon, 31 Dec 2012 19:36:25 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFW00JL05G0TP80@mmp1.samsung.com>; Mon, 31 Dec 2012 19:36:25 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH V3 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor Date: Mon, 31 Dec 2012 05:58:16 -0500 Message-id: <1356951500-22490-6-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> References: <1356951500-22490-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkSndl1sMAg21/VC0err/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlTJn+h7ngr0TFky/3GBsY94p0MXJySAiYSMxZ384G YYtJXLi3Hsjm4hASWMoo8fDaATaYotY7V5lAbCGBRYwSN1r1IYp6mSQWT/vN0sXIwcEmoCrx a7E9SI2IgIHE9CfbWUHCzAIFEs92i4GEhQVcJJbdPcoCYrMAVR9uuQ1WwivgIfHgszPEJjmJ D3sesYPYnAKeEqe37GCG2OohcbN7ITtEq4DEt8mHwJZKCMhKbDrADHKMhMBtNonrj78zQ8yR lDi44gbLBEbhBYwMqxhFUwuSC4qT0nMN9YoTc4tL89L1kvNzNzECA/H0v2dSOxhXNlgcYhTg YFTi4eViehggxJpYVlyZe4hRgoNZSYT3rRZQiDclsbIqtSg/vqg0J7X4EKMP0CUTmaVEk/OB UZJXEm9obGJuamxqaWRkZmqKQ1hJnLfZIyVASCA9sSQ1OzW1ILUIZhwTB6dUA+P5N6c4ojzm NZtGH1RLeFHddLdv4YWeNtbmFf9ZrmbuLj6+MXbb/VcbhAV+7OGZFfX581cm1Sb+N688v75m u7yomXv7wz0vfYO/mW1Ke3DHMak9eoVAaldK6329dce8n6h97FuUvp5rd9HKw3PqFxXOnKHx 957JrPZLwVVsDRIz47X/pQZUXNigxFKckWioxVxUnAgAE0tRVHECAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42I5/e+xgO7KrIcBBvteSFo8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzJgy/Q9zwV+J iidf7jE2MO4V6WLk5JAQMJFovXOVCcIWk7hwbz0biC0ksIhR4karfhcjF5DdyySxeNpvli5G Dg42AVWJX4vtQWpEBAwkpj/ZzgoSZhYokHi2WwwkLCzgIrHs7lEWEJsFqPpwy22wEl4BD4kH n50hNslJfNjziB3E5hTwlDi9ZQczxFYPiZvdC9knMPIuYGRYxSiaWpBcUJyUnmuoV5yYW1ya l66XnJ+7iREc5s+kdjCubLA4xCjAwajEw8vF9DBAiDWxrLgy9xCjBAezkgjvWy2gEG9KYmVV alF+fFFpTmrxIUYfoKMmMkuJJucDYzCvJN7Q2MTc1NjU0sTCxMwSh7CSOG+zR0qAkEB6Yklq dmpqQWoRzDgmDk6pBsa5Szza17wVarkS8jT5Lu9z32Xa+VdLuTbIi3eUNx7Xu/5JYQGz+ORd 3qu1yx7dvT1rY4zQ1/KOVC91pwPSMq5GsTe9H+08njPlGJOdctrRlPyNVcrd/D/qT5ptCVnT sPPRmfD+1SbXfuzqXBshzeu+0PNa4F2LE8l1JvGSbOpuq5i5hYuf9yuxFGckGmoxFxUnAgAq uxJ0oAIAAA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkZ/W83dwo+YGYj5Eykv5hCEExAuTjXSqGMzvPmsSwlMf7jiHGOXBFVreiH1utWHNRcFN7F This API computes the divisor value based on MPLL clock and writes it into the FSYS1 register. Changes from V1: 1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Signed-off-by: Amar --- arch/arm/cpu/armv7/exynos/clock.c | 38 ++++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 4 ++++ 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 973b84e..cd42689 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -659,6 +659,40 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: set the mmc clock div ratio in fsys1 */ +int exynos5_mmc_set_clk_div(int dev_id) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + */ + if (dev_id <= PERIPH_ID_SDMMC1) + addr = (unsigned int)&clk->div_fsys1; + else + addr = (unsigned int)&clk->div_fsys2; + + tmp = readl(addr) & ~FSYS1_MMC0_DIV_MASK; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..2fd7c3e 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,9 @@ #define VPLL 4 #define BPLL 5 +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); @@ -36,6 +39,7 @@ unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); unsigned long get_mmc_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +int exynos5_mmc_set_clk_div(int dev_index); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);