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[203.254.224.25]) by mx.google.com with ESMTP id y9si32768525paw.159.2012.12.28.07.30.48; Fri, 28 Dec 2012 07:30:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFQ00FKXZ2XGR70@mailout2.samsung.com>; Sat, 29 Dec 2012 00:30:47 +0900 (KST) Received: from epcpdlpp24 ( [172.20.52.124]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 0B.DE.12699.72BBDD05; Sat, 29 Dec 2012 00:30:47 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-8e-50ddbb27398d Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id CA.DE.12699.72BBDD05; Sat, 29 Dec 2012 00:30:47 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFQ008MSZ2SO710@mmp2.samsung.com>; Sat, 29 Dec 2012 00:30:47 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH 4/9] EXYNOS5: DWMMC: Added dt support for DWMMC Date: Fri, 28 Dec 2012 10:52:47 -0500 Message-id: <1356709972-26549-5-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1356709972-26549-1-git-send-email-amarendra.xt@samsung.com> References: <1356709972-26549-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsWyRsSkRld9990Ag2mb9Cwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlbPxXUjBXr6L91RW2BsYJql2MHBwSAiYSXd/ruhg5 gUwxiQv31rN1MXJxCAnMYpS49/oNO0zN7FdOEPHpjBJt+94wQzi9TBIPz0xjAyliE1CV+LXY HmSQiICBxPQn21lBwswCBRLPdouBhIUF7CW2b+thArFZgKqn7N7NDmLzCnhINB1uYIe4QU7i w55HYDangKfEo2eLmEFsIaCaq5t2sUH0Ckh8m3yIBeI0WYlNB8CukRC4zSaxouEhK8QcSYmD K26wTGAUXsDIsIpRNLUguaA4KT3XSK84Mbe4NC9dLzk/dxMjMAxP/3smvYNxVYPFIUYBDkYl Ht5FPXcChFgTy4orcw8xSnAwK4nw9jXfDRDiTUmsrEotyo8vKs1JLT7E6AN0yURmKdHkfGCM 5JXEGxqbmJsam1oaGZmZmuIQVhLnbfZICRASSE8sSc1OTS1ILYIZx8TBKdXAuGmWUU+X8O23 62rmrXsppq5idNL3H/vruJ5N1jtv6i+cq6hcqpPy8NzF0BRz9VXdXZd2JDmG1jT/qM7Q+5nR HnvYxfGM5Mzdfg9nC/447VPrmmu368mDefNONfBUOr/h+Fct/yJ6a7njg5TTFn9dHtY9/T9F q+7nrmeboq617gnmf7H0aJSaqxJLcUaioRZzUXEiAPWOi0hwAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42I5/e+xoK767rsBBst71Cwerr/JYjHl8BcW ByaPO9f2sAUwRjUw2mSkJqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4 BOi6ZeYAzVZSKEvMKQUKBSQWFyvp22GaEBripmsB0xih6xsSBNdjZIAGEtYwZmz8V1IwV6+i /dUVtgbGCapdjBwcEgImErNfOXUxcgKZYhIX7q1n62Lk4hASmM4o0bbvDTOE08sk8fDMNDaQ BjYBVYlfi+1BGkQEDCSmP9nOChJmFiiQeLZbDCQsLGAvsX1bDxOIzQJUPWX3bnYQm1fAQ6Lp cAM7xC45iQ97HoHZnAKeEo+eLWIGsYWAaq5u2sU2gZF3ASPDKkbR1ILkguKk9FwjveLE3OLS vHS95PzcTYzgMH8mvYNxVYPFIUYBDkYlHt5FPXcChFgTy4orcw8xSnAwK4nw9jXfDRDiTUms rEotyo8vKs1JLT7E6AN01URmKdHkfGAM5pXEGxqbmJsam1qaWJiYWeIQVhLnbfZICRASSE8s Sc1OTS1ILYIZx8TBKdXA6PtmbdzxzdfOJHGcMjDYXbK068ecxdZvakLYaztbjNaXv79YnHHq b+lvJt0k6bnKjodvvm+VdJ+39PJ/l3tioZ+7Yq29Wd7d/Gh+MOnRhq4ZR2uXLwhtOLDZ0eMj X0z0trVZ31e1z1oTxl414wbnEots85ULZgeqGFz4nO+6uWbhM3sx34oJ05VYijMSDbWYi4oT AZk/vOOgAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQnK+6y2e1rS6pRx5qwnzq3Xj2nfCp6d2KSNcYwuZktOjGD/De56e9sZDLRdo4SH36P89WX1 This patch adds dt support for DWMMC, by reading the dwmmc node data from the device tree and initialising dwmmc channels as per data obtained from the node. Signed-off-by: Vivek Gautam Signed-off-by: Amar --- arch/arm/include/asm/arch-exynos/dwmmc.h | 12 ++-- drivers/mmc/exynos_dw_mmc.c | 116 +++++++++++++++++++++++++++++-- include/dwmmc.h | 4 ++ 3 files changed, 119 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 8acdf9b..39cd4c7 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,10 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) -int exynos_dwmci_init(u32 regbase, int bus_width, int index); +#define FSYS1_MMC0_DIV_VAL 0x0701 + +#ifdef CONFIG_OF_CONTROL +unsigned int exynos_dwmmc_init(const void *blob); +#endif -static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return exynos_dwmci_init(base, bus_width, index); -} +int exynos_dwmci_init(u32 regbase, int bus_width, int index); diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..541889f 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,141 @@ */ #include -#include #include +#include +#include +#include #include #include +#include + +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001 static char *EXYNOS_NAME = "EXYNOS DWMMC"; +u32 timing[3]; +/* + * Function used as callback function to initialise the + * CLKSEL register for every mmc channel. + */ static void exynos_dwmci_clksel(struct dwmci_host *host) { - u32 val; - val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | - DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0); + dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); +} - dwmci_writel(host, DWMCI_CLKSEL, val); +unsigned int exynos_dwmci_get_clk(int dev_index) +{ + return get_mmc_clk(dev_index); } int exynos_dwmci_init(u32 regbase, int bus_width, int index) { struct dwmci_host *host = NULL; + int dev_id = 0; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; } + /* Convert index into corresponding peripheral ID */ + dev_id = index + PERIPH_ID_SDMMC0; + + /* set the clock divisor - clk_div_fsys for mmc */ + if (exynos5_mmc_set_clk_div(dev_id)) { + debug("mmc clock div set failed\n"); + return -1; + } host->name = EXYNOS_NAME; host->ioaddr = (void *)regbase; host->buswidth = bus_width; +#ifdef CONFIG_OF_CONTROL + host->clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); +#else + if (0 == index) + host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; + if (2 == index) + host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; +#endif host->clksel = exynos_dwmci_clksel; host->dev_index = index; - - add_dwmci(host, 52000000, 400000); + host->mmc_clk = exynos_dwmci_get_clk; + /* Add the mmc chennel to be registered with mmc core */ + add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); return 0; } +#ifdef CONFIG_OF_CONTROL +unsigned int exynos_dwmmc_init(const void *blob) +{ + u32 base; + int index, bus_width; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0; + int dev_id, flag; + int count, i; + + count = fdtdec_find_aliases_for_id(blob, "dwmmc", + COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, + DWMMC_MAX_CH_NUM); + + for (i = 0; i < count; i++) { + int node = node_list[i]; + + if (node <= 0) + continue; + + /* Extract device id for each mmc channel */ + dev_id = pinmux_decode_periph_id(blob, node); + + /* Get the bus width from the device node */ + bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (bus_width < 0) { + debug("DWMMC: Can't get bus-width\n"); + return -1; + } + if (8 == bus_width) + flag = PINMUX_FLAG_8BIT_MODE; + else + flag = PINMUX_FLAG_NONE; + + /* config pinmux for each mmc channel */ + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("DWMMC not configured\n"); + return err; + } + + index = dev_id - PERIPH_ID_SDMMC0; + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -1; + } + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", + timing, 3); + if (err) { + debug("Can't get sdr-timings for divider\n"); + return -1; + } + /* Initialise each mmc channel */ + err = exynos_dwmci_init(base, bus_width, index); + if (err) { + debug("Can't do dwmci init\n"); + return -1; + } + } + + return 0; +} +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..4a42849 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) + #define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +147,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth; + u32 clksel_val; u32 fifoth_val; struct mmc *mmc;