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[203.254.224.33]) by mx.google.com with ESMTP id wu8si31877005pbc.243.2012.12.28.04.04.50; Fri, 28 Dec 2012 04:04:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MFQ005EDPK2SNY0@mailout3.samsung.com>; Fri, 28 Dec 2012 21:04:50 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 32.E2.01231.2EA8DD05; Fri, 28 Dec 2012 21:04:50 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-cf-50dd8ae24f7a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id E1.E2.01231.1EA8DD05; Fri, 28 Dec 2012 21:04:50 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MFQ00MRYPFC8100@mmp2.samsung.com>; Fri, 28 Dec 2012 21:04:49 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, l.majewski@samsung.com Subject: [PATCH 2/4] EXYNOS: Add functions for power initialisation Date: Fri, 28 Dec 2012 17:38:43 +0530 Message-id: <1356696525-21001-3-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1356696525-21001-1-git-send-email-rajeshwari.s@samsung.com> References: <1356696525-21001-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWyRsSkVvdR190Ag0W/BSwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlHJ3gXPBXoKJjy2y2Bsa9fF2MHBwSAiYS63cadDFy ApliEhfurWfrYuTiEBJYyiix5Op+RoiEicS6vTtZIBLTGSUeLDwLVTWRSeLl/dvMIFVsAkYS W09OA+sQEZCQ+NV/FcxmFiiR+PatmxXEFhZwlvjfcYUJxGYRUJX4f3UOG4jNK+Ah0XLwLhvE NgWJY1O/gtVzCnhKHHt4DWyOEFDN18OrWSF6BSS+TT7EAvGBrMSmA8wg90gI3GaT+HPkCSvE HEmJgytusExgFF7AyLCKUTS1ILmgOCk911CvODG3uDQvXS85P3cTIzAYT/97JrWDcWWDxSFG AQ5GJR7ehT13AoRYE8uKK3MPMUpwMCuJ8PY13w0Q4k1JrKxKLcqPLyrNSS0+xOgDdMlEZinR 5HxgpOSVxBsam5ibGptaGhmZmZriEFYS5232SAkQEkhPLEnNTk0tSC2CGcfEwSnVwDhz2y3T QxZrb1Tdvj2dYR1fn/VB4S+cD/pEKtpjVSXlE172ywTf+MbzJErtXq18RZxr25bmpRyqUXFS +Rp1nRyLGnrvmR1a5Cwl/OJiVcFt5ZCWRS4nN12wKk9pj5p/Z1KLyZ6Wi7MTRK3tXdi2Wglt LQzot7wyO+160pzJzZG3ez6dFbprp8RSnJFoqMVcVJwIAIkg1odzAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsVy+t9jQd1HXXcDDCY3s1o8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzDg6wbngr0BF x5bZbA2Me/m6GDk5JARMJNbt3ckCYYtJXLi3nq2LkYtDSGA6o8SDhWehnIlMEi/v32YGqWIT MJLYenIaI4gtIiAh8av/KpjNLFAi8e1bNyuILSzgLPG/4woTiM0ioCrx/+ocNhCbV8BDouXg XTaIbQoSx6Z+BavnFPCUOPbwGtgcIaCar4dXs05g5F3AyLCKUTS1ILmgOCk911CvODG3uDQv XS85P3cTIzjYn0ntYFzZYHGIUYCDUYmHd2HPnQAh1sSy4srcQ4wSHMxKIrx9zXcDhHhTEiur Uovy44tKc1KLDzH6AF01kVlKNDkfGIl5JfGGxibmpsamliYWJmaWOISVxHmbPVIChATSE0tS s1NTC1KLYMYxcXBKNTAe++6xoPf6RN2kl26BMq9qPvVI/qnY+/nDriy+d8IfrLg+Mj6+tVVZ 0sqMTd/f2UazoPzZVBdBH37hGZt3v6ixrfk9d9vzhzJhK03W5ppka2j9PbbjSN3abJNvoTEm Z8209ocnScckKh88cC6/R0zvopr0jl927b9jHijkzovzfPXscsyL6+5KLMUZiYZazEXFiQA4 GdKuowIAAA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQmNT8tw41xqhq3cXgeNbiKRJRvdlLT+Wd7RyewP2A88uCuVyfqAqpImbRe8xQWclbun3FLE This patch adds functions to intialsise power registers during spl boot. Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/power.c | 34 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 5 ++++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index d4bce6d..8ab43f4 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -22,8 +22,15 @@ */ #include +#include +#include #include #include +#include +#include +#include +#include +#include static void exynos4_mipi_phy_control(unsigned int dev_index, unsigned int enable) @@ -95,3 +102,30 @@ void set_dp_phy_ctrl(unsigned int enable) if (cpu_is_exynos5()) exynos5_dp_phy_control(enable); } + +uint32_t power_read_reset_status(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + return power->inform1; +} + +void ps_hold_setup(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Set PS-Hold high */ + setbits_le32(&power->ps_hold_control, + EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); +} + +void power_exit_wakeup(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + typedef void (*resume_func)(void); + + ((resume_func)power->inform0)(); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index d2fdb59..3e83f55 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -864,4 +864,9 @@ void set_dp_phy_ctrl(unsigned int enable); #define EXYNOS_DP_PHY_ENABLE (1 << 0) +#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) + +uint32_t power_read_reset_status(void); +void ps_hold_setup(void); +void power_exit_wakeup(void); #endif