From patchwork Fri Dec 7 10:21:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 13412 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A447023FC0 for ; Fri, 7 Dec 2012 10:22:02 +0000 (UTC) Received: from mail-ie0-f172.google.com (mail-ie0-f172.google.com [209.85.223.172]) by fiordland.canonical.com (Postfix) with ESMTP id 42D16A19721 for ; Fri, 7 Dec 2012 10:22:02 +0000 (UTC) Received: by mail-ie0-f172.google.com with SMTP id c13so720848ieb.31 for ; Fri, 07 Dec 2012 02:22:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=2qG0gnqf1KmhKpKc1zu04fFszncEi2sj82U4pCkpEFA=; b=HuCK5Z0lOt565wb7wogvCzO+c2CVhmHOPdemt6f5iZdVfnlm+zfzxK9U9AtVwhjBmM 1UcRrefprgChf74RqRUQPi+36Yv/yjVypmzN0vR1tZlrq1m2DoHJpyaANfraI0yHeUOq Blp4Hy9eZ6ZckbMOrUMXN/ANUREJg92O1mJh3wwYJW7DHjHLe43iAPZaiRDH0EjO25Ky zOnSK1OOlSxl8in5OM5vThgdaRH2fPc5H6u7d3LB3IhEsb0H9ytjfxvc/m4yr5yFCPuW KxT1nIQVtlUA8JlcJ2xQ+93W+NhR4GXgNv0+1Hj0ynpJXClGfPcCk0M0xaEi/lPzJKG4 IjWQ== Received: by 10.50.42.168 with SMTP id p8mr4457301igl.57.1354875721669; Fri, 07 Dec 2012 02:22:01 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp465411igt; Fri, 7 Dec 2012 02:22:01 -0800 (PST) Received: by 10.68.233.230 with SMTP id tz6mr14559684pbc.36.1354875720932; Fri, 07 Dec 2012 02:22:00 -0800 (PST) Received: from mail-pb0-f52.google.com (mail-pb0-f52.google.com [209.85.160.52]) by mx.google.com with ESMTPS id a9si14721632paz.316.2012.12.07.02.22.00 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 07 Dec 2012 02:22:00 -0800 (PST) Received-SPF: neutral (google.com: 209.85.160.52 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.160.52; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.52 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by mail-pb0-f52.google.com with SMTP id ro2so257954pbb.11 for ; Fri, 07 Dec 2012 02:22:00 -0800 (PST) Received: by 10.66.72.225 with SMTP id g1mr12090791pav.79.1354875720695; Fri, 07 Dec 2012 02:22:00 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id nf9sm6477575pbc.17.2012.12.07.02.21.54 (version=SSLv3 cipher=OTHER); Fri, 07 Dec 2012 02:22:00 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, linaro-dev@lists.linaro.org, patches@linaro.org, Chander Kashyap Subject: [Resend Patch v2 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 Date: Fri, 7 Dec 2012 15:51:26 +0530 Message-Id: <1354875686-31703-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354875686-31703-1-git-send-email-chander.kashyap@linaro.org> References: <1354875686-31703-1-git-send-email-chander.kashyap@linaro.org> X-Gm-Message-State: ALoCoQk6Cn3zvtRgUTdM0KNzuAwsA+cJdBMi0L8XgFzmLD1RI3o/U4PncVwpU41OZUeBStsf7M/a This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap --- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 4db8fd6..cfe1024 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -79,6 +79,67 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4x12_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank res1[0x5]; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank res2[0x2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { + struct s5p_gpio_bank res1[0x2]; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res2[0x3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res3[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define exynos4x12_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) + #define exynos5_gpio_part1_get_nr(bank, pin) \ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ EXYNOS5_GPIO_PART1_BASE)->bank)) \