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[203.254.224.25]) by mx.google.com with ESMTP id u8si5620092pav.33.2012.11.29.22.23.20; Thu, 29 Nov 2012 22:23:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MEA00G76F2GY3C0@mailout2.samsung.com>; Fri, 30 Nov 2012 15:23:18 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id BC.78.12699.6D058B05; Fri, 30 Nov 2012 15:23:18 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-3b-50b850d6b469 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 4B.78.12699.6D058B05; Fri, 30 Nov 2012 15:23:18 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MEA00GZNF2NX3A0@mmp1.samsung.com>; Fri, 30 Nov 2012 15:23:18 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, l.majewski@samsung.com, kmpark@infradead.org Subject: [PATCH] EXYNOS5: Add L2 Cache Support. Date: Fri, 30 Nov 2012 11:59:35 +0530 Message-id: <1354256975-24720-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWyRsSkTvdawI4Agy+7LCwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlHP2VW3CUu+Lw02aWBsYDnF2MnBwSAiYSdyd9ZISw xSQu3FvP1sXIxSEksJRRYtXTVSwwRV2b9zNBJBYxSrxes4EFwpnIJPG/sw2snU3ASGLryWlg toiAhMSv/quMIEXMAl2MEje/PAcbJSygL9G1dAI7iM0ioCqxcMckZhCbV8BD4ufZKewQ6xQk jk39ygpRIyDxbfIhoF4OoLisxKYDzCAzJQQOsElcOHeBGaJeUuLgihssExgFFzAyrGIUTS1I LihOSs810itOzC0uzUvXS87P3cQIDLDT/55J72Bc1WBxiFGAg1GJh5dhzfYAIdbEsuLK3EOM EhzMSiK8+wR3BAjxpiRWVqUW5ccXleakFh9i9AG6ZCKzlGhyPjD480riDY1NzE2NTS2NjMxM TXEIK4nzNnukBAgJpCeWpGanphakFsGMY+LglGpgtDiscoH31ecJRYxiE2OcZlcceyEttTi7 3jF4kuNcR9lkzvr7K72vp1zKSr9l2bT2UsHq1sn35GQuaKl7f0plFw7xMH/HWFZpsPfaMTbx 4IRV0+rYCsKveuofeHhUdc6FFesefV8U47Xi7Y1NtaVu6y0TufjXhX1SkKuJTfom2H/A6rSo snKKEktxRqKhFnNRcSIAUnih/l0CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsVy+t9jAd1rATsCDBa81LF4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmHH0V27BUe6K w0+bWRoYD3B2MXJySAiYSHRt3s8EYYtJXLi3nq2LkYtDSGARo8TrNRtYIJyJTBL/O9sYQarY BIwktp6cBmaLCEhI/Oq/yghSxCzQxShx88tzFpCEsIC+RNfSCewgNouAqsTCHZOYQWxeAQ+J n2ensEOsU5A4NvUr6wRG7gWMDKsYRVMLkguKk9JzjfSKE3OLS/PS9ZLzczcxgsP3mfQOxlUN FocYBTgYlXh4GdZsDxBiTSwrrsw9xCjBwawkwrtPcEeAEG9KYmVValF+fFFpTmrxIUYfoO0T maVEk/OBsZVXEm9obGJuamxqaWJhYmaJQ1hJnLfZIyVASCA9sSQ1OzW1ILUIZhwTB6dUAyP3 hDWLWm4aqXUl7zyafXd7/e8l+5XfFPlUTHVXLFolnRX+YDV7eKzmlem/3d1kfA4ZHaxe9yeM v8HSSSLxXlK9ttgZWdfMlyem6q20q1p09LTVTgsLpkmzdZ+dCkhvCQh2T1m7J2W1VtzCnqeh sYpBL/eUVR2SEjSM4L/+Z8cq5rombTsBNiWW4oxEQy3mouJEAOYn0heMAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkIXRYe6eMDgoSVBOi9jHTZ7DcE9ykG2jdk9QbBCgtJGf45WVGJlGNezuZmdcPxlgyzJwzb This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/soc.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index ab65b8d..676a388 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -23,6 +23,14 @@ #include #include +#include + +enum l2_cache_params { + CACHE_TAG_RAM_SETUP = (1<<9), + CACHE_DATA_RAM_SETUP = (1<<5), + CACHE_TAG_RAM_LATENCY = (2<<6), + CACHE_DATA_RAM_LATENCY = (2<<0) +}; void reset_cpu(ulong addr) { @@ -36,3 +44,32 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Set L2 cache parameters + */ +static void exynos5_set_l2cache_params(void) +{ + unsigned int val = 0; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY | + CACHE_DATA_RAM_LATENCY; + + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); +} + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ + if (cpu_is_exynos5()) + exynos5_set_l2cache_params(); +} +#endif +