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[203.254.224.25]) by mx.google.com with ESMTP id s9si16059374pav.1.2012.10.22.23.47.00; Mon, 22 Oct 2012 23:47:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCC00D8M2TICNT0@mailout2.samsung.com>; Tue, 23 Oct 2012 15:46:59 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 8D.68.12699.36D36805; Tue, 23 Oct 2012 15:46:59 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-38-50863d630cc2 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 1D.68.12699.36D36805; Tue, 23 Oct 2012 15:46:59 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCC00CQ52Q0V720@mmp1.samsung.com>; Tue, 23 Oct 2012 15:46:59 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 4/9 V3] EXYNOS: Add I2S registers Date: Tue, 23 Oct 2012 12:27:24 +0530 Message-id: <1350975449-27816-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1350975449-27816-1-git-send-email-rajeshwari.s@samsung.com> References: <1350975449-27816-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkWjfZti3A4OIJFYuH62+yWEw5/IXF gcnjzrU9bAGMUVw2Kak5mWWpRfp2CVwZR86dZSs4IFZx594+5gbGWUJdjJwcEgImEkdWv2GG sMUkLtxbz9bFyMUhJLCUUeJm803WLkYOsKJzU9Mg4osYJTqfH2IDaRASmMgkMaHFGMRmEzCS 2HpyGiOILSIgIfGr/yqYzSwQI/F6/w+wemEBQ4kVR1+xg9gsAqoSPw8fAIvzCnhITHvfyA5x hILEsalfWUFsTgFPibWHzrOA3CAEVLPvZClEq4DEt8mHWCBOk5XYdADq/NtsEn0rqyFsSYmD K26wTGAUXsDIsIpRNLUguaA4KT3XSK84Mbe4NC9dLzk/dxMjMBBP/3smvYNxVYPFIUYBDkYl Ht6O/a0BQqyJZcWVuYcYJTiYlUR4G6zaAoR4UxIrq1KL8uOLSnNSiw8x+gAdMpFZSjQ5Hxgl eSXxhsYm5qbGppZGRmampjiElcR5mz1SAoQE0hNLUrNTUwtSi2DGMXFwSjUwhq7uvGbSrqHi ledwnm/Tyq1Cmi8ecNgeaq8Jrstm3qXLv1l030IzCRn+G1Pmdim5s8u+jaz84e/OXZMt1H1n s5Fb290As13Hl33qmSvWfqd3tkHw199JfnrWutynGZOzShbmijT+2Nv9+tLqVSozHxnoRmV0 b/CrYzv4RyCTc8O5dREl9jeVWIozEg21mIuKEwEg197icQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeLIzCtJLcpLzFFi42I5/e+xgG6ybVuAQedZCYuH62+yWEw5/IXF gcnjzrU9bAGMUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+ AbpumTlAs5UUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGUfOnWUrOCBW cefePuYGxllCXYwcHBICJhLnpqZ1MXICmWISF+6tZ+ti5OIQEljEKNH5/BAbSEJIYCKTxIQW YxCbTcBIYuvJaYwgtoiAhMSv/qtgNrNAjMTr/T/A6oUFDCVWHH3FDmKzCKhK/Dx8ACzOK+Ah Me19IzvEMgWJY1O/soLYnAKeEmsPnWcBuUcIqGbfydIJjLwLGBlWMYqmFiQXFCel5xrpFSfm Fpfmpesl5+duYgQH+jPpHYyrGiwOMQpwMCrx8Hbsbw0QYk0sK67MPcQowcGsJMLbYNUWIMSb klhZlVqUH19UmpNafIjRB+ioicxSosn5wCjMK4k3NDYxNzU2tTSxMDGzxCGsJM7b7JESICSQ nliSmp2aWpBaBDOOiYNTqoFRr9FDuUzFl1n/2mrOCHkXVl7PgkW3vO59iVUrj+/1vT6NbaOE 60+DIiWmg9PKcu/z6+w5eDMjhP1onmPo78vP1Hal6VV83a07tXHZRSfZntiIJAWh9hWp9wRf CLySmNmvU3Pw+wvlkGIX7yUBfmsci1mauM7NVjpjJ3LHRoRPOEktokirWImlOCPRUIu5qDgR ACaryDGhAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQmQtnX6F4olTmNtAZ+qxbGQghZNaEMC6wg7Rpkc5iqzm4/SZQQo2/Nxi9sFqu6BfRhWxKwl This patch add I2S registers Signed-off-by: R. Chandrasekar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - None Changes in V3: - None arch/arm/include/asm/arch-exynos/i2s-regs.h | 66 +++++++++++++++++++++++++++ 1 files changed, 66 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/i2s-regs.h diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h new file mode 100644 index 0000000..2326ca0 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __I2S_REGS_H__ +#define __I2S_REGS_H__ + +#define CON_TXFIFO_FULL (1 << 8) +#define CON_TXCH_PAUSE (1 << 4) +#define CON_ACTIVE (1 << 0) + +#define MOD_BLCP_SHIFT 24 +#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) +#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) +#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) +#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) + +#define MOD_BLC_16BIT (0 << 13) +#define MOD_BLC_8BIT (1 << 13) +#define MOD_BLC_24BIT (2 << 13) +#define MOD_BLC_MASK (3 << 13) + +#define MOD_SLAVE (1 << 11) +#define MOD_MASK (3 << 8) +#define MOD_LR_LLOW (0 << 7) +#define MOD_LR_RLOW (1 << 7) +#define MOD_SDF_IIS (0 << 5) +#define MOD_SDF_MSB (1 << 5) +#define MOD_SDF_LSB (2 << 5) +#define MOD_SDF_MASK (3 << 5) +#define MOD_RCLK_256FS (0 << 3) +#define MOD_RCLK_512FS (1 << 3) +#define MOD_RCLK_384FS (2 << 3) +#define MOD_RCLK_768FS (3 << 3) +#define MOD_RCLK_MASK (3 << 3) +#define MOD_BCLK_32FS (0 << 1) +#define MOD_BCLK_48FS (1 << 1) +#define MOD_BCLK_16FS (2 << 1) +#define MOD_BCLK_24FS (3 << 1) +#define MOD_BCLK_MASK (3 << 1) + +#define MOD_CDCLKCON (1 << 12) + +#define FIC_TXFLUSH (1 << 15) +#define FIC_RXFLUSH (1 << 7) + +#endif /* __I2S_REGS_H__ */