From patchwork Mon Oct 15 11:58:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 12225 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 13AB51D5116 for ; Mon, 15 Oct 2012 11:58:16 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 9B871A1906D for ; Mon, 15 Oct 2012 11:58:15 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so7436497iej.11 for ; Mon, 15 Oct 2012 04:58:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=/juqgqI8VM8heldk5iyO5Qn91S6vUEakaXw43Nc3W5U=; b=Nuw27kXUblBdMWX4u2bBi7ea08KICMwqZDGwRRJ1dDwabrUf0AS9V/ClIk6rRiYEEH ENWUzmAmDYlsvEfaXhCrrcp/131AXvjF7qO4wmptMiNGBnVg6YSXKzFhiMPJOlyZm7DT IEiPxqggN/1R07dj5wNEM3hFR1G9liCJVEU2mQehOYKOnpuWHQdJ/pZE/hpBBA7QtcO+ FsCoWcnOAbrBg+Nlh99/8POibT1aqlE7+l4eVNrXesoRgS7ZvC+kD0fTMMWFayZRoIDU cuqSDtV3748gJcv+uViiy/xzIvDk+EIL/+ZnZ5BTP75Req4jzBHonT+Uz00Gq58IVi3t 11MQ== Received: by 10.50.87.134 with SMTP id ay6mr8309652igb.70.1350302294863; Mon, 15 Oct 2012 04:58:14 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp564041igt; Mon, 15 Oct 2012 04:58:14 -0700 (PDT) Received: by 10.68.190.197 with SMTP id gs5mr36939518pbc.124.1350302293663; Mon, 15 Oct 2012 04:58:13 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id gk10si22131116pbc.266.2012.10.15.04.58.13 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 04:58:13 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by mail-pb0-f50.google.com with SMTP id md4so5404363pbc.37 for ; Mon, 15 Oct 2012 04:58:13 -0700 (PDT) Received: by 10.68.216.2 with SMTP id om2mr35951986pbc.88.1350302293138; Mon, 15 Oct 2012 04:58:13 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id tt6sm8970472pbc.51.2012.10.15.04.58.10 (version=SSLv3 cipher=OTHER); Mon, 15 Oct 2012 04:58:12 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, linaro-dev@lists.linaro.org, patches@linaro.org, Chander Kashyap Subject: [PATCH v2] EXYNOS: Clock: Add common function for pll rate calculation Date: Mon, 15 Oct 2012 17:28:00 +0530 Message-Id: <1350302280-4987-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQlI/MsJ7tnJCsBt3qpnDL+Z0S3MvOLhUn1Hygg/NKUN1ygOnL1u6qr3iEW2xRAMNx0TxdP4 From: Minkyu Kang Moved the common code to calculate pll clock rate to new function exynos_get_pll_clk(). Signed-off-by: Chander Kashyap --- Changes from v1: - Author name changed arch/arm/cpu/armv7/exynos/clock.c | 102 ++++++++++++++----------------------- 1 file changed, 38 insertions(+), 64 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..a042423 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,41 +26,19 @@ #include #include -/* exynos4: return pll clock frequency */ -static unsigned long exynos4_get_pll_clk(int pllreg) +/* exynos: return pll clock frequency */ +static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long r, m, p, s, k = 0, mask, fout; + unsigned long m, p, s = 0, mask, fout; unsigned int freq; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - /* * APLL_CON: MIDV [25:16] * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -92,13 +70,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; } +/* exynos4: return pll clock frequency */ +static unsigned long exynos4_get_pll_clk(int pllreg) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, fout_sel; + unsigned long r, k = 0, fout; + unsigned int pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -123,41 +131,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return 0; } - /* - * APLL_CON: MIDV [25:16] - * MPLL_CON: MIDV [25:16] - * EPLL_CON: MIDV [24:16] - * VPLL_CON: MIDV [24:16] - * BPLL_CON: MIDV [25:16] - */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) - mask = 0x3ff; - else - mask = 0x1ff; - - m = (r >> 16) & mask; - - /* PDIV [13:8] */ - p = (r >> 8) & 0x3f; - /* SDIV [2:0] */ - s = r & 0x7; - - freq = CONFIG_SYS_CLK_FREQ; - - if (pllreg == EPLL) { - k = k & 0xffff; - /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 65536) * (freq / (p * (1 << s))); - } else if (pllreg == VPLL) { - k = k & 0xfff; - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 1024) * (freq / (p * (1 << s))); - } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); - } + fout = exynos_get_pll_clk(pllreg, r, k); /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/