From patchwork Tue Oct 2 12:57:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 11917 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1638923EF8 for ; Tue, 2 Oct 2012 12:57:53 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id BBFA6A1869F for ; Tue, 2 Oct 2012 12:57:52 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so14025584iej.11 for ; Tue, 02 Oct 2012 05:57:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=8LfrV0+375vc33exNQ6AvMwaBD5UqfUWCbGNSvj3N2U=; b=p3v55wWwk2ECUVoRpoWKit2uq1jXW2nFLo0P4sZxAYiccGwO/y7G7QddMudSftCPDf y7FmAXgQGwZ9XeAdgh5XBkg5pM6nLym5rB8cpwaw4jPhtdm/ghDd4+cSVEeGSKqRHqln anezVLS+u5GC+5EovoZzV+k6IGC9Q3KHAif7A9S/eqyF1KFn7GdrNBDh5oClpYaX8i2a J8i6Dgnnb1MOhN5jQuobgTe8HwEYQjxiO/ZkmXjw0bh+hYvc7djqiC8+d8jd4SMXZpKx DrcAiaulJMvIg8bhE2su/O2NuLRv7+G//yscYyi6yJitzDEXVMzQV0N9w8qNg4FTeUNy ztiQ== Received: by 10.50.154.137 with SMTP id vo9mr8033414igb.28.1349182672519; Tue, 02 Oct 2012 05:57:52 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp80700igc; Tue, 2 Oct 2012 05:57:52 -0700 (PDT) Received: by 10.68.224.69 with SMTP id ra5mr4001172pbc.114.1349182671947; Tue, 02 Oct 2012 05:57:51 -0700 (PDT) Received: from mail-da0-f50.google.com (mail-da0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id u7si473852paz.66.2012.10.02.05.57.51 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Oct 2012 05:57:51 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by daez20 with SMTP id z20so2250813dae.37 for ; Tue, 02 Oct 2012 05:57:51 -0700 (PDT) Received: by 10.66.87.73 with SMTP id v9mr7739690paz.1.1349182671605; Tue, 02 Oct 2012 05:57:51 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id m5sm697795pax.10.2012.10.02.05.57.49 (version=SSLv3 cipher=OTHER); Tue, 02 Oct 2012 05:57:51 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, linaro-dev@lists.linaro.org, patches@linaro.org, Chander Kashyap Subject: [PATCH 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 Date: Tue, 2 Oct 2012 18:27:28 +0530 Message-Id: <1349182648-9422-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349182648-9422-1-git-send-email-chander.kashyap@linaro.org> References: <1349182648-9422-1-git-send-email-chander.kashyap@linaro.org> X-Gm-Message-State: ALoCoQn07u0Ak1DzAbBgGFlgmkWvL/5CueTRVZpeSwsrXC7SP4DqyTZ6fBKOeTQUFRxOpC+cpCLW This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap --- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 4db8fd6..47335e7 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -79,6 +79,67 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4x12_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank res1[0x5]; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank res2[0x2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { + struct s5p_gpio_bank res1[0x2]; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res2[0x3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res3[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define exynos4x12_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS5_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) + #define exynos5_gpio_part1_get_nr(bank, pin) \ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ EXYNOS5_GPIO_PART1_BASE)->bank)) \