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[203.254.224.24]) by mx.google.com with ESMTP id pn6si2481334pbb.40.2012.08.13.22.41.10; Mon, 13 Aug 2012 22:41:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M8Q00KAND2KXGO0@mailout1.samsung.com>; Tue, 14 Aug 2012 14:41:10 +0900 (KST) X-AuditID: cbfee61a-b7fc66d0000043b7-96-5029e4f5a2b4 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id B9.B6.17335.5F4E9205; Tue, 14 Aug 2012 14:41:10 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M8Q00064D2QKU20@mmp1.samsung.com>; Tue, 14 Aug 2012 14:41:09 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 4/9] EXYNOS: Add I2S registers Date: Tue, 14 Aug 2012 11:15:27 +0530 Message-id: <1344923132-31803-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1344923132-31803-1-git-send-email-rajeshwari.s@samsung.com> References: <1344923132-31803-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKJMWRmVeSWpSXmKPExsVy+t9jAd1vTzQDDM40MVk8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKePP/IXPBM9GK149fsDYwXhbsYuTkkBAwkXg/9TUb hC0mceHeeiCbi0NIYBGjxIOf05hBEkICE5kk+udpg9hsAkYSW09OYwSxRQQkJH71XwWyOTiY BUolpkzMAwkLC+hJTPm+DCzMIqAq0bClECTMK+Ah0X/mMtQqBYljU7+ygticAp4St64vY4TY 5CGx/t0ZxgmMvAsYGVYxiqYWJBcUJ6XnGuoVJ+YWl+al6yXn525iBHv+mdQOxpUNFocYBTgY lXh4FdI0A4RYE8uKK3MPMUpwMCuJ8N7vAQrxpiRWVqUW5ccXleakFh9ilOZgURLnNfb+6i8k kJ5YkpqdmlqQWgSTZeLglGpgnOi9+eHmImcJ9k17bRR7WsLjrXY5VXGavfF7lVVgWnm/UaSU 3+e0Ia/AkmNqwdzq3MfXHdNsP/J+nmHv0Z/MwpbztiTcF1pdXqrOtb6qZee0u28dv09PmsAx 98KXHgvT9S9e8s0R5vOOnRGXLG1/5d/EiWfFY5S6OmZceq13kyd7e8b2pVH3lFiKMxINtZiL ihMBd/Xd//gBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQn2K7ssuUj7F+eqSmCUxkanflNGfI4eGTGfVniFhrKS8IZ+wudHJJZnoxcu5o6qUvlQN8wG This patch add I2S registers Signed-off-by: R. Chandrasekar Signed-off-by: Rajeshwari Shinde --- arch/arm/include/asm/arch-exynos/i2s-regs.h | 66 +++++++++++++++++++++++++++ 1 files changed, 66 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/i2s-regs.h diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h new file mode 100644 index 0000000..2326ca0 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * R. Chandrasekar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __I2S_REGS_H__ +#define __I2S_REGS_H__ + +#define CON_TXFIFO_FULL (1 << 8) +#define CON_TXCH_PAUSE (1 << 4) +#define CON_ACTIVE (1 << 0) + +#define MOD_BLCP_SHIFT 24 +#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) +#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) +#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) +#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) + +#define MOD_BLC_16BIT (0 << 13) +#define MOD_BLC_8BIT (1 << 13) +#define MOD_BLC_24BIT (2 << 13) +#define MOD_BLC_MASK (3 << 13) + +#define MOD_SLAVE (1 << 11) +#define MOD_MASK (3 << 8) +#define MOD_LR_LLOW (0 << 7) +#define MOD_LR_RLOW (1 << 7) +#define MOD_SDF_IIS (0 << 5) +#define MOD_SDF_MSB (1 << 5) +#define MOD_SDF_LSB (2 << 5) +#define MOD_SDF_MASK (3 << 5) +#define MOD_RCLK_256FS (0 << 3) +#define MOD_RCLK_512FS (1 << 3) +#define MOD_RCLK_384FS (2 << 3) +#define MOD_RCLK_768FS (3 << 3) +#define MOD_RCLK_MASK (3 << 3) +#define MOD_BCLK_32FS (0 << 1) +#define MOD_BCLK_48FS (1 << 1) +#define MOD_BCLK_16FS (2 << 1) +#define MOD_BCLK_24FS (3 << 1) +#define MOD_BCLK_MASK (3 << 1) + +#define MOD_CDCLKCON (1 << 12) + +#define FIC_TXFLUSH (1 << 15) +#define FIC_RXFLUSH (1 << 7) + +#endif /* __I2S_REGS_H__ */