From patchwork Tue Jul 24 07:23:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 10216 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6695023E56 for ; Tue, 24 Jul 2012 07:18:14 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 288BAA180D6 for ; Tue, 24 Jul 2012 07:18:14 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so6653535ggn.11 for ; Tue, 24 Jul 2012 00:18:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=CbToNTq3eeKUUg4w14XWCaawXsVpt+Y6G+Xw35wMo6w=; b=c3ZwL8kiZ4bzq1R1gUk4G8j+azD+dl62FfPsUvkTaXPS7yVF4RueQ0H/7mob8Ymg6B 7Jv+Jh65Wnoj6FFVPq5oVG3YjJVEU4cETXqJiP9xbRyc2CA2dGX8jiYYrKg+o1rIzpxW 6zSNdkg90X5Wugt/rkT63gRZVbC59sQI4qqyjnENLEPZ/tyI3dgzW+ZWUENEG305/7zK cc1fieTO9bWuUxVtlkqF1XMsvXuVFHgOE0IwslUK+OlLrvILtOtnO6dh5KZebC4E5I1g MLrUwBTYAQoH8CxagubZa2Np0RN+8vqEYSTxDH3bqSem2CQ5Iz4ckx8yDVooavxO4vn+ uy7w== Received: by 10.42.54.133 with SMTP id r5mr8455818icg.9.1343114293747; Tue, 24 Jul 2012 00:18:13 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.153.7 with SMTP id i7csp67679ibw; Tue, 24 Jul 2012 00:18:13 -0700 (PDT) Received: by 10.66.75.97 with SMTP id b1mr2618732paw.15.1343114292953; Tue, 24 Jul 2012 00:18:12 -0700 (PDT) Received: from mailout2.samsung.com (mailout2.samsung.com. [203.254.224.25]) by mx.google.com with ESMTP id ky6si26964133pbc.288.2012.07.24.00.18.12; Tue, 24 Jul 2012 00:18:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7N006BWLLKO8E0@mailout2.samsung.com>; Tue, 24 Jul 2012 16:18:11 +0900 (KST) X-AuditID: cbfee61a-b7f616d000004b7e-52-500e4c335889 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 66.A3.19326.33C4E005; Tue, 24 Jul 2012 16:18:11 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7N0070ELLVCSJ1@mmp1.samsung.com>; Tue, 24 Jul 2012 16:18:11 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 4/8 V7] EXYNOS: PINMUX: Add pinmux support for I2C Date: Tue, 24 Jul 2012 12:53:51 +0530 Message-id: <1343114635-28169-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1343114635-28169-1-git-send-email-rajeshwari.s@samsung.com> References: <1343114635-28169-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jAV1jH74Ag44FChYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgybl87xFJwVbLi0rInjA2MS0W7GDk5JARMJP5PvssO YYtJXLi3nq2LkYtDSGARo0R/5wpWCGcik8ShA61MIFVsAkYSW09OYwSxRQQkJH71X2UEKWIW 2MIocfzVRaB2Dg5hASeJSRNiQGpYBFQl/n68zAgS5hXwkFgzQx1imYLEsalfWUFsTgFPiY3X t4KNFwIqeXrnFOsERt4FjAyrGEVTC5ILipPScw31ihNzi0vz0vWS83M3MYK9/0xqB+PKBotD jAIcjEo8vJmtvAFCrIllxZW5hxglOJiVRHh5PfgChHhTEiurUovy44tKc1KLDzFKc7AoifMa e3/1FxJITyxJzU5NLUgtgskycXBKNTAmLtfMCJ3xac3iWuGoZUX8gRtCf6R8PnrxycQ0hige hXqX1EAbzekWfoemzPnEZF+ceNxUJ3XGv+t9e2TZpJ/VmX6vcrkla/t9csTM2PRp5/hjy8+s jojdOr3xaMoZ/dh3G6reTvxrduyN18UpD1ZXGVpwLjJRbNAs2VfQq1C1fX3M8lZp8V1KLMUZ iYZazEXFiQAwIOSB+gEAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmFvH9AVTcPF21gNDzuD0KEWdkW6rFRKXvp2GWg5uAQtNVyAOVjiVHndQppGJONfNmA8lUQ This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - Aligned the pinmux functionality as per the latest comments. Changes in V3: - None Changes in V4: - None Changes in V5: - None Changes in V6: - None Changes in V7: - None. arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 8 ++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 0e91a6c..7776add 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -188,6 +188,48 @@ static void exynos5_sromc_config(int flags) } } +static void exynos5_i2c_config(int peripheral, int flags) +{ + + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -205,6 +247,16 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SROMC: exynos5_sromc_config(flags); break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos5_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..b861d7d 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,