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[203.254.224.33]) by mx.google.com with ESMTP id vh6si26942062pbc.350.2012.07.24.00.18.06; Tue, 24 Jul 2012 00:18:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7N008X4LLXDOA0@mailout3.samsung.com>; Tue, 24 Jul 2012 16:18:05 +0900 (KST) X-AuditID: cbfee61b-b7f566d000005c8a-f9-500e4c2c155f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 9E.36.23690.C2C4E005; Tue, 24 Jul 2012 16:18:05 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7N0070ELLVCSJ1@mmp1.samsung.com>; Tue, 24 Jul 2012 16:18:04 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 1/8 V7] EXYNOS: CLK: Add i2c clock Date: Tue, 24 Jul 2012 12:53:48 +0530 Message-id: <1343114635-28169-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1343114635-28169-1-git-send-email-rajeshwari.s@samsung.com> References: <1343114635-28169-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAV1dH74Ag7kTWCwerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlHPt8lbWgVaTi7vuPLA2MMwW6GDk5JARMJJ50TmOF sMUkLtxbzwZiCwksYpSYvV2mi5ELyJ7IJHH61jlGkASbgJHE1pPTwGwRAQmJX/1XGUGKmAW2 MEocf3URrFsYqOjW63dgNouAqsSMVYfAbF4BD4m+Iz+ZILYpSByb+hVsM6eAp8TG61uZIDZ7 SDy9c4p1AiPvAkaGVYyiqQXJBcVJ6blGesWJucWleel6yfm5mxjB/n8mvYNxVYPFIUYBDkYl Hl6JLt4AIdbEsuLK3EOMEhzMSiK8vB58AUK8KYmVValF+fFFpTmpxYcYpTlYlMR5Tby/+gsJ pCeWpGanphakFsFkmTg4pRoYF5l3///SJ1m9U2z6GbYlLKEZlzUDb56ae5OdZ0PSYvML/Z5H zrF5XP3sylC4fXumWU9W1rM99ptsH3m87fK9WGcb8z3tmeilZTuKjfa75/0IXfGjP3v7JDH5 eSv237+p7/M9dfOuwspTc9kY/zy/Ghrp38t99d7etE35R/RrM5S++dRKGEXYKbEUZyQaajEX FScCAFRo/LH7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmNYy7qDoGDC/u/oAXqTJ/OrHFbfkn8aF6JFCYxB4m4/7d7e6qP5hS4enTDoJeizrYBI3u0 This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- changes in V2: - Incorporated comments from Simon Glass which are removed extra braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for return statement. Changes in V3: - None Changes in V4: - None Changes in V5: - None. Changes in V6: - Incorporated review comments from Simon Glass. Changes in V7: - None. arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 672598f..de3db8e 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -605,6 +605,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = (readl(&clk->div_top1)) >> 24; + ratio &= 0x7; + aclk_66_pre = sclk / (ratio + 1); + ratio = readl(&clk->div_top0); + ratio &= 0x7; + aclk_66 = aclk_66_pre / (ratio + 1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -621,6 +644,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index e99339a..5529025 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -31,6 +31,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);