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[203.254.224.24]) by mx.google.com with ESMTP id nq4si1921588pbc.192.2012.07.19.04.34.36; Thu, 19 Jul 2012 04:34:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7E00LRCO5BDG10@mailout1.samsung.com>; Thu, 19 Jul 2012 20:34:35 +0900 (KST) X-AuditID: cbfee61a-b7f616d000004b7e-78-5007f0cb7f21 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 8D.33.19326.BC0F7005; Thu, 19 Jul 2012 20:34:35 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7E00GKSO532160@mmp2.samsung.com>; Thu, 19 Jul 2012 20:34:35 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 4/8 V6] EXYNOS: PINMUX: Add pinmux support for I2C Date: Thu, 19 Jul 2012 17:09:57 +0530 Message-id: <1342698001-27683-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1342698001-27683-1-git-send-email-rajeshwari.s@samsung.com> References: <1342698001-27683-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jQd3TH9gDDObMFLN4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CVsXHJXqaCLZIV59uOMDUwThbtYuTkkBAwkXi4s48V whaTuHBvPVsXIxeHkMB0Rolrrx4xQjgTmSRmT7/CDlLFJmAksfXkNEYQW0RAQuJX/1WwImaB LYwSx19dZANJCAs4SZx6togFxGYRUJV4sWs1WJxXwENi6udOqHUKEsemfgWzOQU8JXr33gNb IARUc6R5NeMERt4FjAyrGEVTC5ILipPScw31ihNzi0vz0vWS83M3MYID4JnUDsaVDRaHGAU4 GJV4eDXV2AOEWBPLiitzDzFKcDArifBuuw8U4k1JrKxKLcqPLyrNSS0+xCjNwaIkzmvs/dVf SCA9sSQ1OzW1ILUIJsvEwSnVwOjMs1U+6uCSKb+mF17fe9FxfttGLubHxhfeRZgdXPst5Fta zexpL4xU0x3Nn/2uWMcj+TKtaf+cOz/y3ojpZUhd32gxdfn3Ne9TvjO6HVV33Wa9IvfIzcQ8 T9ZZgSnzCg64iyYfYrnZuHAFTzej44wvrX/YHf7yMu37MOHiKhneNWmrVut/FExSYinOSDTU Yi4qTgQAtSx9UvwBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQntVhCrV+qUKrv0Ltw8/ALJ3hkNJOOlFQaSRCMjH7rm/1jI60cAt097CSWtBysNnpsb3TtM This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - Aligned the pinmux functionality as per the latest comments. Changes in V3: - None Changes in V4: - None Changes in V5: - None Changes in V6: - None arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 8 ++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 0e91a6c..7776add 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -188,6 +188,48 @@ static void exynos5_sromc_config(int flags) } } +static void exynos5_i2c_config(int peripheral, int flags) +{ + + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -205,6 +247,16 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SROMC: exynos5_sromc_config(flags); break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos5_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..b861d7d 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,