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[203.254.224.24]) by mx.google.com with ESMTP id pw3si3839939pbb.211.2012.07.19.04.34.27; Thu, 19 Jul 2012 04:34:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7E00LRCO5BDG10@mailout1.samsung.com>; Thu, 19 Jul 2012 20:34:26 +0900 (KST) X-AuditID: cbfee61a-b7f616d000004b7e-58-5007f0c2eab2 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 74.33.19326.2C0F7005; Thu, 19 Jul 2012 20:34:26 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M7E00GKSO532160@mmp2.samsung.com>; Thu, 19 Jul 2012 20:34:26 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 1/8 V6] EXYNOS: CLK: Add i2c clock Date: Thu, 19 Jul 2012 17:09:54 +0530 Message-id: <1342698001-27683-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1342698001-27683-1-git-send-email-rajeshwari.s@samsung.com> References: <1342698001-27683-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jQd1DH9gDDCbP4bV4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CVseTmKdaCJ8IV83u3MjYwtgt0MXJySAiYSPzftZsd whaTuHBvPVsXIxeHkMB0Rolpe9uZIZyJTBINK+YzglSxCRhJbD05DcwWEZCQ+NV/lRGkiFlg C6PE8VcX2UASwkBFB+d/ZOli5OBgEVCVOPE9CyTMK+Ah0T7rLSvENgWJY1O/gtmcAp4SvXvv gV0hBFRzpHk14wRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLzczcxgv3/TGoH48oGi0OM AhyMSjy8mmrsAUKsiWXFlbmHGCU4mJVEeLfdBwrxpiRWVqUW5ccXleakFh9ilOZgURLnNfb+ 6i8kkJ5YkpqdmlqQWgSTZeLglGpgVDU79PpWfWtkhmG1k0LvPubiuy8+7eCOW31X/8sZtWm/ zLzzRCoeOa5L+bTFMWHlWmbvTac1TTNfaqzLO7bF48XtMw2fXUpnOc6d8Xyz6M2jwSE2spXS jl0WXLc59nonHdblWH1R4HprgciNt6bXbQ/2nixzCy9pu3ftzOIpH194Hn47rWt+rxJLcUai oRZzUXEiADlBtPD7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQlSHE2PRNfHivxmBWFm4hbsK7FvN980pJRJVm+DGLw4Rkk+stiZC2GAxtefJWf9CT2T9oq5 This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass Acked-by: Simon Glass --- changes in V2: - Incorporated comments from Simon Glass which are removed extra braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for return statement. Changes in V3: - None Changes in V4: - None Changes in V5: - None. Changes in V6: - Incorporated review comments from Simon Glass. arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 672598f..de3db8e 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -605,6 +605,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = (readl(&clk->div_top1)) >> 24; + ratio &= 0x7; + aclk_66_pre = sclk / (ratio + 1); + ratio = readl(&clk->div_top0); + ratio &= 0x7; + aclk_66 = aclk_66_pre / (ratio + 1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -621,6 +644,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index e99339a..5529025 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -31,6 +31,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);