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[203.254.224.24]) by mx.google.com with ESMTP id pw9si37602105pbb.47.2012.07.05.04.55.27; Thu, 05 Jul 2012 04:55:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6O001P2RS24K40@mailout1.samsung.com>; Thu, 05 Jul 2012 20:55:26 +0900 (KST) X-AuditID: cbfee61a-b7f616d000004b7e-d1-4ff580ae5955 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 7B.58.19326.EA085FF4; Thu, 05 Jul 2012 20:55:26 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6O00E8SRRY5M50@mmp2.samsung.com>; Thu, 05 Jul 2012 20:55:26 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com Subject: [PATCH 3/7 V5] EXYNOS: PINMUX: Add pinmux support for I2C Date: Thu, 05 Jul 2012 17:29:48 +0530 Message-id: <1341489592-24243-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341489592-24243-1-git-send-email-rajeshwari.s@samsung.com> References: <1341489592-24243-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jQd11DV/9Dd4+0bV4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CVsXX1OuaC2ZIV2+6/YG5gbBLtYuTkkBAwkfiw9yQ7 hC0mceHeerYuRi4OIYHpjBKPfh9nhXAmMkmsmLyUCaSKTcBIYuvJaYwgtoiAhMSv/quMIEXM ArMYJRZtaWQDSQgLOEn0d68Bs1kEVCUets5mAbF5BTwkzv3bxwixTkHi2NSvrCA2p4CnxM/+ Z0D1HEDbPCQuLpaZwMi7gJFhFaNoakFyQXFSeq6hXnFibnFpXrpecn7uJkaw/59J7WBc2WBx iFGAg1GJhzcg66u/EGtiWXFl7iFGCQ5mJRHe3gygEG9KYmVValF+fFFpTmrxIUZpDhYlcV5j b6CUQHpiSWp2ampBahFMlomDU6qBsfHWvywPtefCWwsKFW0UnktzRL/c91FZIm6Wu5l/Sf+W JocDfhPU4m99Ds7cp2d0XV3rymnvv7ahq6peiySkTtDbsX25x4fLp5xPHhHq2v9bsNJq760X i74zC6yabXqN2aV41/rlzZzO1cn/BF0FwjuvV/s9EX7SJXRtdfuO3l1M1VZOAUKcSizFGYmG WsxFxYkAppm1OPsBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmYDs9hBXHKK3GwNIeP8iRJ8G6bOA9elePBlbWD+0kHh9CdEj0ERu8aWsM+RPpN3k4QXdC1 This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - Aligned the pinmux functionality as per the latest comments. Changes in V3: - None Changes in V4: - None Changes in V5: - None arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 8 ++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 822410e..e90ad6a 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -188,6 +188,48 @@ static void exynos5_sromc_config(int flags) } } +static void exynos5_i2c_config(int peripheral, int flags) +{ + + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -205,6 +247,16 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SROMC: exynos5_sromc_config(flags); break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos5_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..b861d7d 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,