From patchwork Wed Jul 4 06:02:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9808 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2E59223E47 for ; Wed, 4 Jul 2012 05:59:37 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id F1E45A18793 for ; Wed, 4 Jul 2012 05:59:36 +0000 (UTC) Received: by mail-gh0-f180.google.com with SMTP id z12so6643805ghb.11 for ; Tue, 03 Jul 2012 22:59:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=goWCp2wSI2dddSecCkPAFpmlhqymu3Fc07I1nfOCcNc=; b=MmdBjR5Z37h2DM8gUoq5dXT7exdLevtwcrPtqs4rHcVTS4NnzCcyg88h8fP5fDun/K MYJT+ghdHaGFQPG72y0SX/oRF5b/rNZ9robaGsqdpF7t1VRds8iLEPtzMTJq3KJSrbWZ 4WqDCQ4wM2J4lcjv/N2hgPY4UPRumPTd8EK0LX61XsXEvz+G6i7XJ/fq4lpEn0HVugZL 47z4yMSkGrLf47bK/6hRM9Dt2RWgIzbqIC4lpiWhBnPgu4mVfZ2OGBLM4QJekhFMffkO +giNGMciytCcpADrp4roIbmiDpSdEWF+xtkAlYqKe0aah8kE9tp3DxbdFURPI/ZrelAD BBaQ== Received: by 10.42.89.72 with SMTP id f8mr10522584icm.33.1341381576514; Tue, 03 Jul 2012 22:59:36 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp49620ibb; Tue, 3 Jul 2012 22:59:36 -0700 (PDT) Received: by 10.68.219.166 with SMTP id pp6mr14876736pbc.35.1341381575853; Tue, 03 Jul 2012 22:59:35 -0700 (PDT) Received: from mailout4.samsung.com (mailout4.samsung.com. [203.254.224.34]) by mx.google.com with ESMTP id wt7si30901249pbc.322.2012.07.03.22.59.35; Tue, 03 Jul 2012 22:59:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6M00MSQGKAGD40@mailout4.samsung.com>; Wed, 04 Jul 2012 14:59:34 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-8c-4ff3dbc6bceb Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id B9.C7.12095.6CBD3FF4; Wed, 04 Jul 2012 14:59:34 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6M00GQYGLOH980@mmp1.samsung.com>; Wed, 04 Jul 2012 14:59:34 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 08/10 V6] EXYNOS5: CLOCK: Add BPLL support Date: Wed, 04 Jul 2012 11:32:58 +0530 Message-id: <1341381780-2725-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341381780-2725-1-git-send-email-rajeshwari.s@samsung.com> References: <1341381780-2725-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jAd1jtz/7G5yYoWLxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoEr49GzNvaCPVIVS1s2sTUwThXtYuTkkBAwkejZ+poF whaTuHBvPVsXIxeHkMAiRomFe++xQjgTmSS2rvzMBlLFJmAksfXkNEYQW0RAQuJX/1VGkCJm gRWMEnN6toGNEhawkph79Bc7iM0ioCox/ep+sDivgLvEz9XPmSHWKUgcm/qVFcTmFPCQaN7y BcwWAqrp2NLGOIGRdwEjwypG0dSC5ILipPRcI73ixNzi0rx0veT83E2M4AB4Jr2DcVWDxSFG AQ5GJR7eG1c++wuxJpYVV+YeYpTgYFYS4b25GyjEm5JYWZValB9fVJqTWnyIUZqDRUmct8n6 gr+QQHpiSWp2ampBahFMlomDU6qBcd5bnkCh44Lpb1duW/D6xIrj35jiD+1Jtrsc039pWtHJ qVcX1pu3tcxI+OfDujP/VdXSvzNzjgvMnnQwMj4o3MzH/I5EdtCJJs7DB9pkb71pnamXP43P L6XdpMbDWt/d4KbDk01HXNcndkuy/K2YPqfx9wIlvjhLkeVyT7itp9z7u3xz6pL1kkosxRmJ hlrMRcWJAIr+KWD8AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkh+FEngdMumtGgEjyVS7S6cotIXxIX1TF4K1owh/fB2npVlIFw1MxNL9slOEKnlmm4GenU This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V3: - New Patch. Changes in V4: - Removed warning message. Changes in V5: - fixed indentation error Changes in V6: - None. arch/arm/cpu/armv7/exynos/clock.c | 28 +++++++++++++++++++++------- arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 2 ++ 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index dbd5f11..fc0ed5e 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, mpll_fout_sel; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } - /* According to the user manual, in EVT1 MPLL always gives + /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL) { + if (pllreg == MPLL || pllreg == BPLL) { pll_div2_sel = readl(&clk->pll_div2_sel); - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) - & MPLL_FOUT_SEL_MASK; - if (mpll_fout_sel == 0) + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + } + + if (fout_sel == 0) fout /= 2; } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..e99339a 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index bf41c19..fce38ef 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -599,4 +599,6 @@ struct exynos5_clock { #define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif