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[203.254.224.25]) by mx.google.com with ESMTP id nc7si31034859pbc.45.2012.07.03.22.59.30; Tue, 03 Jul 2012 22:59:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6M00ATXGM4MO60@mailout2.samsung.com>; Wed, 04 Jul 2012 14:59:29 +0900 (KST) X-AuditID: cbfee61a-b7f086d000000e64-bb-4ff3dbc1f5c6 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 7A.43.03684.1CBD3FF4; Wed, 04 Jul 2012 14:59:29 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6M00GQYGLOH980@mmp1.samsung.com>; Wed, 04 Jul 2012 14:59:29 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 07/10 V6] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 Date: Wed, 04 Jul 2012 11:32:57 +0530 Message-id: <1341381780-2725-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341381780-2725-1-git-send-email-rajeshwari.s@samsung.com> References: <1341381780-2725-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGJMWRmVeSWpSXmKPExsVy+t9jAd2Dtz/7G1zqlLN4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CVce3iDNaC+QIVN9alNjC28XYxcnBICJhITOhS62Lk BDLFJC7cW8/WxcjFISSwiFFix9PDjCAJIYGJTBKfOoxBbDYBI4mtJ6eBxUUEJCR+9V9lBGlg FljBKDGnZxsLSEJYIEJi2a2pzCA2i4CqxLRfh8HivALuEuf+32KF2KYgcWzqVzCbU8BDonnL F1aIZe4SHVvaGCcw8i5gZFjFKJpakFxQnJSea6hXnJhbXJqXrpecn7uJEez7Z1I7GFc2WBxi FOBgVOLhtb7y2V+INbGsuDL3EKMEB7OSCO/N3UAh3pTEyqrUovz4otKc1OJDjNIcLErivE3W F/yFBNITS1KzU1MLUotgskwcnFINjIGr2BbUS9y5e72bz/v89Q/nzoY8YPOW0epjrTiTa9u8 QGvLvUn1548ufFqobsViwJTjdrc3fBKTX4lblX/UnTNyF64+cmoz/rOr/1fnxXXTW5fvKFpr ybQmrnYeR8T+Svd/iikpZeErsv/LvpqsOEmBZZWFjfqMzL8rjIQzzcJP7am/Mq+8WomlOCPR UIu5qDgRAJoNa9f5AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmBfGDrSHFyHELCpV79ytESWU2vMWdiQty02hMwj2WXYgmAD9BVxrkwsve38UZH7N9vfKyu MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V2: - None Changes in V3: - Incorported review comments from Minkyu Kang. Changes in V4: - None. Changes in V5: - None Changes in V6: - None arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1..bf41c19 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif