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[203.254.224.25]) by mx.google.com with ESMTP id hs8si11841762pbc.250.2012.07.02.04.33.39; Mon, 02 Jul 2012 04:33:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6J005UX6S2IBB0@mailout2.samsung.com>; Mon, 02 Jul 2012 20:33:38 +0900 (KST) X-AuditID: cbfee61a-b7f086d000000e64-f3-4ff18712d0ec Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 4B.60.03684.21781FF4; Mon, 02 Jul 2012 20:33:38 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6J00MOX6QL8K70@mmp2.samsung.com>; Mon, 02 Jul 2012 20:33:38 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 08/10 V5] EXYNOS5: CLOCK: Add BPLL support Date: Mon, 02 Jul 2012 17:06:43 +0530 Message-id: <1341229005-19008-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341229005-19008-1-git-send-email-rajeshwari.s@samsung.com> References: <1341229005-19008-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jQV2h9o/+BnffqVg8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKmN98nbFgkVTFylbpBsZm0S5GTg4JAROJtd/Xs0DY YhIX7q1n62Lk4hASmM4o8f/pARYIZyKTxKyds8Gq2ASMJLaenMYIYosISEj86r/KCFLELLCC UWJOzzawImEBK4kt/3uZQWwWAVWJCacOgsV5BTwkFje3skGsU5A4NvUrK4jNKeApMePyZDBb CKjmVtcB5gmMvAsYGVYxiqYWJBcUJ6XnGuoVJ+YWl+al6yXn525iBPv/mdQOxpUNFocYBTgY lXh4HzR/9BdiTSwrrsw9xCjBwawkwrshASjEm5JYWZValB9fVJqTWnyIUZqDRUmct8n6gr+Q QHpiSWp2ampBahFMlomDU6qBcU6RXedbmS0f3LofH3TNe/hinutW6UxpzbLXd9dd3J70JcHx +pfrvz0F9t+9Z5z5VV2pr37bjM02T0ov+oWeVn6yP/fYw6BVlYY+8fHcF+QWOCWnq8lnTO5l uC914de0c+Ffrvtmdl3/esvzSY7n3h9++TVWTtouoselGdPiou7t/a28jPfXKyWW4oxEQy3m ouJEADfPTa/7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkefeLJ38q+9MmhUv435z15sca1qwdgWkM0ZRaOh165yHE+OI3Bw5DnWQyzVJtout/hD68B This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V3: - New Patch. Changes in V4: - Removed warning message. Changes in V5: - fixed indentation error arch/arm/cpu/armv7/exynos/clock.c | 28 +++++++++++++++++++++------- arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 2 ++ 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index dbd5f11..fc0ed5e 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, mpll_fout_sel; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } - /* According to the user manual, in EVT1 MPLL always gives + /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL) { + if (pllreg == MPLL || pllreg == BPLL) { pll_div2_sel = readl(&clk->pll_div2_sel); - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) - & MPLL_FOUT_SEL_MASK; - if (mpll_fout_sel == 0) + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + } + + if (fout_sel == 0) fout /= 2; } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..e99339a 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index bf41c19..fce38ef 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -599,4 +599,6 @@ struct exynos5_clock { #define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif