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[203.254.224.24]) by mx.google.com with ESMTP id sp1si21311366pbc.50.2012.07.02.04.33.19; Mon, 02 Jul 2012 04:33:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6J00EW26PTHXO0@mailout1.samsung.com>; Mon, 02 Jul 2012 20:33:18 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-bf-4ff186fe6096 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 5D.83.12095.EF681FF4; Mon, 02 Jul 2012 20:33:18 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6J00MOX6QL8K70@mmp2.samsung.com>; Mon, 02 Jul 2012 20:33:18 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com, jh80.chung@samsung.com Subject: [PATCH 04/10 V5] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 Date: Mon, 02 Jul 2012 17:06:39 +0530 Message-id: <1341229005-19008-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341229005-19008-1-git-send-email-rajeshwari.s@samsung.com> References: <1341229005-19008-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jQd1/bR/9DU6eE7V4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CV8W3TS8aCp0kVO2ftZWpgnB3YxcjBISFgInHip2wX IyeQKSZx4d56ti5GLg4hgemMEosvtrFAOBOZJK5vamIEqWITMJLYenIamC0iICHxq/8qI0gR s8AKRok5PdtYQBLCAikSsz5cAbNZBFQl/l/6wARi8wp4SBzduIQRYp2CxLGpX1lBbE4BT4kZ lyeD2UJANbe6DjBPYORdwMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93EyPY/8+kdzCuarA4 xCjAwajEw/uv/qO/EGtiWXFl7iFGCQ5mJRHeDQlAId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rxN 1hf8hQTSE0tSs1NTC1KLYLJMHJxSDYzSmjwfLDew/ahM1I1/+7nyVdYShQ13D/EemhwTET61 QPqk6GPHf2zGaQKTTO7nNPy84SO9bXXEqcV827dNPqUio3f4YJSw99U9Pb+P7fo2KWgVw1QW zwB2wQvH78ZFfgt6sDKhONQiaV+Ep2Pw5UTb7Sp669QWZd+4GCRs/H7N8akXLq/YnvlDiaU4 I9FQi7moOBEADw03i/sBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQnMsNCZ3ifPrT8cExbbsRtOzrhBoujg8kCTW8jVPT2E//VAKSesWsdG88tiNPgLaNHqQbLU Define additional registers for clock control in Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V2: - None. Changes in V3: - Modified Clocks as per Exynos5250 Rev 1.0. Changes in V4: - None. Changes in V5: - None arch/arm/include/asm/arch-exynos/clock.h | 234 ++++++++++++++++-------------- 1 files changed, 126 insertions(+), 108 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 50da958..90271f1 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -273,8 +273,7 @@ struct exynos5_clock { unsigned int clkout_cmu_cpu_div_stat; unsigned char res8[0x5f8]; unsigned int armclk_stopctrl; - unsigned int atclk_stopctrl; - unsigned char res9[0x8]; + unsigned char res9[0x0c]; unsigned int parityfail_status; unsigned int parityfail_clear; unsigned char res10[0x8]; @@ -323,259 +322,278 @@ struct exynos5_clock { unsigned char res19[0xf8]; unsigned int div_core0; unsigned int div_core1; - unsigned char res20[0xf8]; + unsigned int div_sysrgt; + unsigned char res20[0xf4]; unsigned int div_stat_core0; unsigned int div_stat_core1; - unsigned char res21[0x2f8]; + unsigned int div_stat_sysrgt; + unsigned char res21[0x2f4]; unsigned int gate_ip_core; - unsigned char res22[0xfc]; + unsigned int gate_ip_sysrgt; + unsigned char res22[0x8]; + unsigned int c2c_monitor; + unsigned char res23[0xec]; unsigned int clkout_cmu_core; unsigned int clkout_cmu_core_div_stat; - unsigned char res23[0x5f8]; + unsigned char res24[0x5f8]; unsigned int dcgidx_map0; unsigned int dcgidx_map1; unsigned int dcgidx_map2; - unsigned char res24[0x14]; + unsigned char res25[0x14]; unsigned int dcgperf_map0; unsigned int dcgperf_map1; - unsigned char res25[0x18]; + unsigned char res26[0x18]; unsigned int dvcidx_map; - unsigned char res26[0x1c]; + unsigned char res27[0x1c]; unsigned int freq_cpu; unsigned int freq_dpm; - unsigned char res27[0x18]; + unsigned char res28[0x18]; unsigned int dvsemclk_en; unsigned int maxperf; - unsigned char res28[0x3478]; + unsigned char res29[0xf78]; + unsigned int c2c_config; + unsigned char res30[0x24fc]; unsigned int div_acp; - unsigned char res29[0xfc]; + unsigned char res31[0xfc]; unsigned int div_stat_acp; - unsigned char res30[0x1fc]; + unsigned char res32[0x1fc]; unsigned int gate_ip_acp; - unsigned char res31[0x1fc]; + unsigned char res33[0xfc]; + unsigned int div_syslft; + unsigned char res34[0xc]; + unsigned int div_stat_syslft; + unsigned char res35[0x1c]; + unsigned int gate_ip_syslft; + unsigned char res36[0xcc]; unsigned int clkout_cmu_acp; unsigned int clkout_cmu_acp_div_stat; - unsigned char res32[0x38f8]; + unsigned char res37[0x8]; + unsigned int ufmc_config; + unsigned char res38[0x38ec]; unsigned int div_isp0; unsigned int div_isp1; unsigned int div_isp2; - unsigned char res33[0xf4]; + unsigned char res39[0xf4]; unsigned int div_stat_isp0; unsigned int div_stat_isp1; unsigned int div_stat_isp2; - unsigned char res34[0x3f4]; + unsigned char res40[0x3f4]; unsigned int gate_ip_isp0; unsigned int gate_ip_isp1; - unsigned char res35[0xf8]; + unsigned char res41[0xf8]; unsigned int gate_sclk_isp; - unsigned char res36[0xc]; + unsigned char res42[0xc]; unsigned int mcuisp_pwr_ctrl; - unsigned char res37[0xec]; + unsigned char res43[0xec]; unsigned int clkout_cmu_isp; unsigned int clkout_cmu_isp_div_stat; - unsigned char res38[0x3618]; + unsigned char res44[0x3618]; unsigned int cpll_lock; - unsigned char res39[0xc]; + unsigned char res45[0xc]; unsigned int epll_lock; - unsigned char res40[0xc]; + unsigned char res46[0xc]; unsigned int vpll_lock; - unsigned char res41[0xdc]; + unsigned char res47[0xc]; + unsigned int gpll_lock; + unsigned char res48[0xcc]; unsigned int cpll_con0; unsigned int cpll_con1; - unsigned char res42[0x8]; + unsigned char res49[0x8]; unsigned int epll_con0; unsigned int epll_con1; unsigned int epll_con2; - unsigned char res43[0x4]; + unsigned char res50[0x4]; unsigned int vpll_con0; unsigned int vpll_con1; unsigned int vpll_con2; - unsigned char res44[0xc4]; + unsigned char res51[0x4]; + unsigned int gpll_con0; + unsigned int gpll_con1; + unsigned char res52[0xb8]; unsigned int src_top0; unsigned int src_top1; unsigned int src_top2; unsigned int src_top3; unsigned int src_gscl; - unsigned int src_disp0_0; - unsigned int src_disp0_1; + unsigned char res53[0x8]; unsigned int src_disp1_0; - unsigned int src_disp1_1; - unsigned char res46[0xc]; + unsigned char res54[0x10]; unsigned int src_mau; unsigned int src_fsys; - unsigned char res47[0x8]; + unsigned int src_gen; + unsigned char res55[0x4]; unsigned int src_peric0; unsigned int src_peric1; - unsigned char res48[0x18]; + unsigned char res56[0x18]; unsigned int sclk_src_isp; - unsigned char res49[0x9c]; + unsigned char res57[0x9c]; unsigned int src_mask_top; - unsigned char res50[0xc]; + unsigned char res58[0xc]; unsigned int src_mask_gscl; - unsigned int src_mask_disp0_0; - unsigned int src_mask_disp0_1; + unsigned char res59[0x8]; unsigned int src_mask_disp1_0; - unsigned int src_mask_disp1_1; - unsigned int src_mask_maudio; - unsigned char res52[0x8]; + unsigned char res60[0x4]; + unsigned int src_mask_mau; + unsigned char res61[0x8]; unsigned int src_mask_fsys; - unsigned char res53[0xc]; + unsigned int src_mask_gen; + unsigned char res62[0x8]; unsigned int src_mask_peric0; unsigned int src_mask_peric1; - unsigned char res54[0x18]; + unsigned char res63[0x18]; unsigned int src_mask_isp; - unsigned char res55[0x9c]; + unsigned char res67[0x9c]; unsigned int mux_stat_top0; unsigned int mux_stat_top1; unsigned int mux_stat_top2; unsigned int mux_stat_top3; - unsigned char res56[0xf0]; + unsigned char res68[0xf0]; unsigned int div_top0; unsigned int div_top1; - unsigned char res57[0x8]; + unsigned char res69[0x8]; unsigned int div_gscl; - unsigned int div_disp0_0; - unsigned int div_disp0_1; + unsigned char res70[0x8]; unsigned int div_disp1_0; - unsigned int div_disp1_1; - unsigned char res59[0x8]; + unsigned char res71[0xc]; unsigned int div_gen; - unsigned char res60[0x4]; + unsigned char res72[0x4]; unsigned int div_mau; unsigned int div_fsys0; unsigned int div_fsys1; unsigned int div_fsys2; - unsigned int div_fsys3; + unsigned char res73[0x4]; unsigned int div_peric0; unsigned int div_peric1; unsigned int div_peric2; unsigned int div_peric3; unsigned int div_peric4; unsigned int div_peric5; - unsigned char res61[0x10]; + unsigned char res74[0x10]; unsigned int sclk_div_isp; - unsigned char res62[0xc]; + unsigned char res75[0xc]; unsigned int div2_ratio0; unsigned int div2_ratio1; - unsigned char res63[0x8]; + unsigned char res76[0x8]; unsigned int div4_ratio; - unsigned char res64[0x6c]; + unsigned char res77[0x6c]; unsigned int div_stat_top0; unsigned int div_stat_top1; - unsigned char res65[0x8]; + unsigned char res78[0x8]; unsigned int div_stat_gscl; - unsigned int div_stat_disp0_0; - unsigned int div_stat_disp0_1; + unsigned char res79[0x8]; unsigned int div_stat_disp1_0; - unsigned int div_stat_disp1_1; - unsigned char res67[0x8]; + unsigned char res80[0xc]; unsigned int div_stat_gen; - unsigned char res68[0x4]; - unsigned int div_stat_maudio; + unsigned char res81[0x4]; + unsigned int div_stat_mau; unsigned int div_stat_fsys0; unsigned int div_stat_fsys1; unsigned int div_stat_fsys2; - unsigned int div_stat_fsys3; + unsigned char res82[0x4]; unsigned int div_stat_peric0; unsigned int div_stat_peric1; unsigned int div_stat_peric2; unsigned int div_stat_peric3; unsigned int div_stat_peric4; unsigned int div_stat_peric5; - unsigned char res69[0x10]; + unsigned char res83[0x10]; unsigned int sclk_div_stat_isp; - unsigned char res70[0xc]; + unsigned char res84[0xc]; unsigned int div2_stat0; unsigned int div2_stat1; - unsigned char res71[0x8]; + unsigned char res85[0x8]; unsigned int div4_stat; - unsigned char res72[0x180]; - unsigned int gate_top_sclk_disp0; + unsigned char res86[0x184]; unsigned int gate_top_sclk_disp1; unsigned int gate_top_sclk_gen; - unsigned char res74[0xc]; + unsigned char res87[0xc]; unsigned int gate_top_sclk_mau; unsigned int gate_top_sclk_fsys; - unsigned char res75[0xc]; + unsigned char res88[0xc]; unsigned int gate_top_sclk_peric; - unsigned char res76[0x1c]; + unsigned char res89[0x1c]; unsigned int gate_top_sclk_isp; - unsigned char res77[0xac]; + unsigned char res90[0xac]; unsigned int gate_ip_gscl; - unsigned int gate_ip_disp0; + unsigned char res91[0x4]; unsigned int gate_ip_disp1; unsigned int gate_ip_mfc; unsigned int gate_ip_g3d; unsigned int gate_ip_gen; - unsigned char res79[0xc]; + unsigned char res92[0xc]; unsigned int gate_ip_fsys; - unsigned char res80[0x4]; - unsigned int gate_ip_gps; + unsigned char res93[0x8]; unsigned int gate_ip_peric; - unsigned char res81[0xc]; + unsigned char res94[0xc]; unsigned int gate_ip_peris; - unsigned char res82[0x1c]; + unsigned char res95[0x1c]; unsigned int gate_block; - unsigned char res83[0x7c]; + unsigned char res96[0x1c]; + unsigned int mcuiop_pwr_ctrl; + unsigned char res97[0x5c]; unsigned int clkout_cmu_top; unsigned int clkout_cmu_top_div_stat; - unsigned char res84[0x37f8]; + unsigned char res98[0x37f8]; unsigned int src_lex; - unsigned char res85[0x2fc]; + unsigned char res99[0x1fc]; + unsigned int mux_stat_lex; + unsigned char res100[0xfc]; unsigned int div_lex; - unsigned char res86[0xfc]; + unsigned char res101[0xfc]; unsigned int div_stat_lex; - unsigned char res87[0x1fc]; + unsigned char res102[0x1fc]; unsigned int gate_ip_lex; - unsigned char res88[0x1fc]; + unsigned char res103[0x1fc]; unsigned int clkout_cmu_lex; unsigned int clkout_cmu_lex_div_stat; - unsigned char res89[0x3af8]; + unsigned char res104[0x3af8]; unsigned int div_r0x; - unsigned char res90[0xfc]; + unsigned char res105[0xfc]; unsigned int div_stat_r0x; - unsigned char res91[0x1fc]; + unsigned char res106[0x1fc]; unsigned int gate_ip_r0x; - unsigned char res92[0x1fc]; + unsigned char res107[0x1fc]; unsigned int clkout_cmu_r0x; unsigned int clkout_cmu_r0x_div_stat; - unsigned char res94[0x3af8]; + unsigned char res108[0x3af8]; unsigned int div_r1x; - unsigned char res95[0xfc]; + unsigned char res109[0xfc]; unsigned int div_stat_r1x; - unsigned char res96[0x1fc]; + unsigned char res110[0x1fc]; unsigned int gate_ip_r1x; - unsigned char res97[0x1fc]; + unsigned char res111[0x1fc]; unsigned int clkout_cmu_r1x; unsigned int clkout_cmu_r1x_div_stat; - unsigned char res98[0x3608]; + unsigned char res112[0x3608]; unsigned int bpll_lock; - unsigned char res99[0xfc]; + unsigned char res113[0xfc]; unsigned int bpll_con0; unsigned int bpll_con1; - unsigned char res100[0xe8]; + unsigned char res114[0xe8]; unsigned int src_cdrex; - unsigned char res101[0x1fc]; + unsigned char res115[0x1fc]; unsigned int mux_stat_cdrex; - unsigned char res102[0xfc]; + unsigned char res116[0xfc]; unsigned int div_cdrex; - unsigned int div_cdrex2; - unsigned char res103[0xf8]; + unsigned char res117[0xfc]; unsigned int div_stat_cdrex; - unsigned char res104[0x2fc]; + unsigned char res118[0x2fc]; unsigned int gate_ip_cdrex; - unsigned char res105[0xc]; - unsigned int c2c_monitor; - unsigned int dmc_pwr_ctrl; - unsigned char res106[0x4]; + unsigned char res119[0x10]; + unsigned int dmc_freq_ctrl; + unsigned char res120[0x4]; unsigned int drex2_pause; - unsigned char res107[0xe0]; + unsigned char res121[0xe0]; unsigned int clkout_cmu_cdrex; unsigned int clkout_cmu_cdrex_div_stat; - unsigned char res108[0x8]; + unsigned char res122[0x8]; unsigned int lpddr3phy_ctrl; - unsigned char res109[0xf5f8]; + unsigned int lpddr3phy_con0; + unsigned int lpddr3phy_con1; + unsigned int lpddr3phy_con2; + unsigned int lpddr3phy_con3; + unsigned int pll_div2_sel; + unsigned char res123[0xf5d8]; }; #endif - #endif