From patchwork Fri Jun 29 12:59:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9716 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id BC4BA23E40 for ; Fri, 29 Jun 2012 12:56:29 +0000 (UTC) Received: from mail-yw0-f47.google.com (mail-yw0-f47.google.com [209.85.213.47]) by fiordland.canonical.com (Postfix) with ESMTP id 8C8E4A18749 for ; Fri, 29 Jun 2012 12:56:29 +0000 (UTC) Received: by mail-yw0-f47.google.com with SMTP id j56so3346442yhj.20 for ; Fri, 29 Jun 2012 05:56:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=IKrgZM45pAyGbepCWUeNbXoH2sqfin83FDF4A092ojQ=; b=E7h0ENDSvHo74AB1M43oOnRiIalI/iwLhKkQ1Z+/EAE3Mp9dCqIXsdnu1kWfd9Mu2X PFPUnbRdiiF9Gbi6dPX4V1YBTBaNmHEmT9yp3WOAaAoFxH2MLfPRds688c6MGcoYnuJB Ay7iaAZMUoWrVv2YXqmAYX3pMrqJy0eelUZl2p+oAbtyWylolYbjkLwMfqRGD4rM6Qz7 1B6tpYA7OO72zwW+jTUH+TadSyZ46N3WYZFvgE6nV4T6YlSLam3nQqJiSTyrgi3CtM4C ilSr+nRLDx0ySWMCDG4F32u3BYGUc5TLv/iSlOCesCJLQIamC0sdkvAVY9VZlm+/92qk 1ROw== Received: by 10.50.203.39 with SMTP id kn7mr948165igc.53.1340974589178; Fri, 29 Jun 2012 05:56:29 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp90919ibb; Fri, 29 Jun 2012 05:56:26 -0700 (PDT) Received: by 10.68.240.69 with SMTP id vy5mr6029376pbc.156.1340974586315; Fri, 29 Jun 2012 05:56:26 -0700 (PDT) Received: from mailout3.samsung.com (mailout3.samsung.com. [203.254.224.33]) by mx.google.com with ESMTP id tg7si8308894pbc.39.2012.06.29.05.56.25; Fri, 29 Jun 2012 05:56:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00AI4QJYLLE0@mailout3.samsung.com>; Fri, 29 Jun 2012 21:56:13 +0900 (KST) X-AuditID: cbfee61a-b7f086d000000e64-e8-4feda5ec7d30 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 3B.2E.03684.CE5ADEF4; Fri, 29 Jun 2012 21:56:12 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00JE7QK7T260@mmp2.samsung.com>; Fri, 29 Jun 2012 21:56:12 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, alim.akhtar@samsung.com, dofmind@gmail.com, jh80.chung@samsung.com Subject: [PATCH 07/10 V4] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 Date: Fri, 29 Jun 2012 18:29:07 +0530 Message-id: <1340974750-19969-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> References: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jQd03S9/6GzT3W1g8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKePnpHmPBRv6K00e+sDYwbuHpYuTkkBAwkZi6/Dcj hC0mceHeerYuRi4OIYHpjBLLfrUwQTgTmSReXjrAClLFJmAksfXkNLAOEQEJiV/9VxlBipgF FjFK3O35xQ6SEBaIkPh7rAmogYODRUBV4tZbT5Awr4CHxO0X/1khtilIHJv6FczmFPCUeLKp CcwWAqp58eYi6wRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLzczcxgv3/TGoH48oGi0OM AhyMSjy8FUve+guxJpYVV+YeYpTgYFYS4X24GCjEm5JYWZValB9fVJqTWnyIUZqDRUmct8n6 gr+QQHpiSWp2ampBahFMlomDU6qBcXHZ/uinF80WCoVWOTFXsS6P3cv41ornXstRuTdTTBn4 XS9MU1siGev+TCnr9z2bOZNEhZ+JyLpLdNzbn+4xQ90wZOHFLuO4J2vSrYM+uhzdftyKP9uD IezF3gt7BR5+WSRv8cpgbe+uB0q7Fh5fY/Om48ekF++5+6Yt9y2yOzQ1eWoWb6LVBCWW4oxE Qy3mouJEANU7J+f7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQl5d7TRcASNtnUZaKgesI5wgYBX5Eu/HpiuRbUfldvuCwhAD5Bel7iW8ZyQSx0Yx9APU3KJ MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V2: - None Changes in V3: - Incorported review comments from Minkyu Kang. Changes in V4: - None arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1..bf41c19 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif