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[203.254.224.25]) by mx.google.com with ESMTP id ub6si7922086pbc.337.2012.06.29.04.57.58; Fri, 29 Jun 2012 04:57:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00EY3NUV15F0@mailout2.samsung.com>; Fri, 29 Jun 2012 20:57:57 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-df-4fed98450877 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 98.A4.12095.5489DEF4; Fri, 29 Jun 2012 20:57:57 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00HDINUORD90@mmp1.samsung.com>; Fri, 29 Jun 2012 20:57:57 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, alim.akhtar@samsung.com, dofmind@gmail.com, jh80.chung@samsung.com Subject: [PATCH 07/10 V3] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 Date: Fri, 29 Jun 2012 17:30:37 +0530 Message-id: <1340971240-18373-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> References: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jAV3XGW/9DXbe0rd4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CV8fDWCtaCZv6Kk6f3sDcwLubpYuTkkBAwkfj09jgT hC0mceHeerYuRi4OIYFFjBLHei6xQzgTmSRaWk+ygFSxCRhJbD05jRHEFhGQkPjVf5URpIgZ pONuzy92kISwQITEg+m/2EBsFgFVieXHe5lBbF4BD4nt83rYINYpSByb+pUVxOYU8JSYPnsF WI0QUM2Zx8dYJjDyLmBkWMUomlqQXFCclJ5rpFecmFtcmpeul5yfu4kRHADPpHcwrmqwOMQo wMGoxMMr0vrWX4g1say4MvcQowQHs5II74oWoBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeJusL /kIC6YklqdmpqQWpRTBZJg5OqQbGbUe//9TbuuwB07HL1jHr4jaaCM2d/kZLfKfNQhaJwk3Z Wi0Fsw/8agnhOh4dHpiW02lt03LUMtpgfRdjWJX1hu01RpvZDtc/+LfX1/WJg+gx/p68DcVn 2o2/Zl3R/e24a3X1ptLEJaeflJ3esOHnDfOi4p3R2/QrtMq75Z+7HxTa7e7k8/m3EktxRqKh FnNRcSIAmsEup/wBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkS66yFaS8o8t9D9Zu+lg/PWlYjFu7e+m3oddEVUlgmtplgJ3FugcgN5ChkkZVXpuHRb+in MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None Changes in V3: - Incorported review comments from Minkyu Kang. arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1..bf41c19 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif