From patchwork Fri Jun 29 12:00:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9706 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5F48623E01 for ; Fri, 29 Jun 2012 11:58:16 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 2FC6AA18543 for ; Fri, 29 Jun 2012 11:58:16 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id q6so2855716yen.11 for ; Fri, 29 Jun 2012 04:58:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=ZIqJnKK7jr6Gtd64DJ741R/72ItisRgvvKn+erjO3iw=; b=PuJa/NYUk8NOzICEJj17vZstNAATy9ynsEottMUPmhW7qY4TLxuMJk3zK4WaV2mCNG Hu09uXwKCoQ7QUk72Ydr1lXdccJhUM0SDTdJnItjrL9fZWmctKs4/jgCUBG4MwmDoQIk 3MYdKOtXhrmm6v9FJA2gcoxKhCYS5yeb4SjTyIGVLXtWVinukYtoSDnOGOKgfcLyh6UO mAf/q2QsPV4aIKrKbNHqD3VyDb0Xddeytq1E3OhlnWab8Q0/c4WVz59fK+yidvovi7UQ ngR6oFO8JtGpg02OmIxgcEWnLGF5ch9SQ8uMKx+xhnzmbrdiCpO6H7EhOlMmrzC4Mcs3 sPKA== Received: by 10.50.203.39 with SMTP id kn7mr797457igc.53.1340971095769; Fri, 29 Jun 2012 04:58:15 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp88357ibb; Fri, 29 Jun 2012 04:58:15 -0700 (PDT) Received: by 10.66.72.225 with SMTP id g1mr608397pav.3.1340971094821; Fri, 29 Jun 2012 04:58:14 -0700 (PDT) Received: from mailout2.samsung.com (mailout2.samsung.com. [203.254.224.25]) by mx.google.com with ESMTP id nc7si8019076pbc.195.2012.06.29.04.58.14; Fri, 29 Jun 2012 04:58:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00EY3NUV15F0@mailout2.samsung.com>; Fri, 29 Jun 2012 20:58:13 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-11-4fed98553c87 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id A4.B4.12095.5589DEF4; Fri, 29 Jun 2012 20:58:13 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00HDINUORD90@mmp1.samsung.com>; Fri, 29 Jun 2012 20:58:13 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, alim.akhtar@samsung.com, dofmind@gmail.com, jh80.chung@samsung.com Subject: [PATCH 09/10 V3] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 Date: Fri, 29 Jun 2012 17:30:39 +0530 Message-id: <1340971240-18373-10-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> References: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAd3QGW/9DeauUbJ4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CV0TjhJmPBQomKyfM+sTQw7hfuYuTgkBAwkbjyQa6L kRPIFJO4cG89WxcjF4eQwCJGiRPdk1khnIlMEq+nLWQGqWITMJLYenIaI4gtIiAh8av/KiNI ETNIx92eX+wgCWGBcIkdO1+wgdgsAqoSEx9fBrN5BTwlLs89ywyxTkHi2NSvrCA2J1B8+uwV YHEhAQ+JM4+PsUxg5F3AyLCKUTS1ILmgOCk910ivODG3uDQvXS85P3cTI9j/z6R3MK5qsDjE KMDBqMTDK9L61l+INbGsuDL3EKMEB7OSCO+KFqAQb0piZVVqUX58UWlOavEhRmkOFiVx3ibr C/5CAumJJanZqakFqUUwWSYOTqkGRq/DPCf4Z+0LNSvP2rfqmUKTwpXnK/PKhJkuM/MadNkY 7tr4J6jf7RGjQtDZ6KkWR2VkloaVpb+RnRpSq7vLRf/qy23bRKuZg3Slr811aQ22uPBBNmr+ c+ZE9q1SsXG+2xfp5E5d2LnsV2u9X/CSlWuP5nULcJn9W3al9drKvzcO6d5Xuv5KWYmlOCPR UIu5qDgRAPeHt7r7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmqIvJqM7/AYUGH57VFOoLKrM0y9TFZiSD9oJSiBvRx5tPiMiOfEgznafUr6hQGI4KJwRt0 This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None. Changes in V3: - Corrected the pinmux settings and offset calcuation of gpio banks. arch/arm/cpu/armv7/exynos/pinmux.c | 22 +++++++++++++--------- arch/arm/include/asm/arch-exynos/gpio.h | 7 +++++-- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..822410e 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral) count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + bank = &gpio1->d0; + start = 0; count = 4; break; case PERIPH_ID_UART2: @@ -66,23 +66,27 @@ static int exynos5_mmc_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start, gpio_func; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; + start = 0; + gpio_func = GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c1; + bank = &gpio1->c2; bank_ext = NULL; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c2; - bank_ext = &gpio1->c3; + bank = &gpio1->c3; + bank_ext = &gpio1->c4; + start = 3; + gpio_func = GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c3; + bank = &gpio1->c4; bank_ext = NULL; break; } @@ -92,8 +96,8 @@ static int exynos5_mmc_config(int peripheral, int flags) return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); } diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 7a9bb90..97be4ea 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -100,7 +100,9 @@ struct exynos5_gpio_part1 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x980]; + struct s5p_gpio_bank res1[0x3]; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank res2[0x48]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2; @@ -122,9 +124,10 @@ struct exynos5_gpio_part2 { struct exynos5_gpio_part3 { struct s5p_gpio_bank v0; struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; struct s5p_gpio_bank v2; struct s5p_gpio_bank v3; - struct s5p_gpio_bank res1[0x20]; + struct s5p_gpio_bank res2[0x1]; struct s5p_gpio_bank v4; };