From patchwork Wed Jun 20 10:40:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9472 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 10CF823F2A for ; Wed, 20 Jun 2012 10:36:27 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id D3C75A185B9 for ; Wed, 20 Jun 2012 10:36:26 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so5941773ggn.11 for ; Wed, 20 Jun 2012 03:36:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=dxnj1e+c3XhDmUPsyO9F/6899UJUl+EqPuoV18Lv5x4=; b=D6TOgL62MDCic94Zh/0dcaI54PP6b7F4jxud+ZO+wQOu3uQRirOZVNLmOPegGTtTUq 5lQP4rr5z9Ky2TVwbsgcELQTmVJTusu2f2f9iWXhBZ4bc78NdVlZT9lPIeke8arhhnaf YWEhcUZ5t1YM+EjJc1QSkZmk9is7p5+m8URB03/Ye+ohPXBxpp6thqJeR5+B1Uz/hDe4 cmUHQ0QuTyI1JRkDqmN5rm4Q2dCl1bue4LGhYxyc4hCemlw3U2e8PuvAE6nNMtvG915X WRBI4U9g6BgXyPUcH3PGQFfL/J+x1rvANcqiz9H8Lu6+N9arivFWveFqA4BGZBV7mK6V mhTA== Received: by 10.50.203.39 with SMTP id kn7mr3925344igc.53.1340188586302; Wed, 20 Jun 2012 03:36:26 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp172734ibb; Wed, 20 Jun 2012 03:36:25 -0700 (PDT) Received: by 10.50.171.98 with SMTP id at2mr3941385igc.26.1340188585662; Wed, 20 Jun 2012 03:36:25 -0700 (PDT) Received: from mailout2.samsung.com (mailout2.samsung.com. [203.254.224.25]) by mx.google.com with ESMTP id pv10si18079975pbb.4.2012.06.20.03.36.25; Wed, 20 Jun 2012 03:36:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W000WKW390T20@mailout2.samsung.com>; Wed, 20 Jun 2012 19:36:20 +0900 (KST) X-AuditID: cbfee61b-b7fcc6d000003a7a-5d-4fe1a7a40719 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id E6.B2.14970.4A7A1EF4; Wed, 20 Jun 2012 19:36:20 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00HP6W2XTK70@mmp1.samsung.com>; Wed, 20 Jun 2012 19:36:20 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com, banajit.g@samsung.com Subject: [PATCH 4/9] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 Date: Wed, 20 Jun 2012 16:10:05 +0530 Message-id: <1340188810-18871-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> References: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jAd0lyx/6G+w5pGvxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoEr4+GH2oJm6Yqb566zNzAuFeti5OSQEDCRWNy6gBnC FpO4cG89WxcjF4eQwCJGicMzjzJCOBOZJC5/38ICUsUmYCSx9eQ0RhBbREBC4lf/VbAiZoGF jBITZt4EGyUsEC9xfcFRIJuDg0VAVWLLUw+QMK+Ah8S12Z9ZIbYpSByb+hXM5hTwlJh2ZhfY fCGgmufnL7FPYORdwMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93EyPY+8+kdzCuarA4xCjA wajEw3tizkN/IdbEsuLK3EOMEhzMSiK85R1AId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rxN1hf8 hQTSE0tSs1NTC1KLYLJMHJxSDYwpOxZOSn8heXO13duVeg/btwvmnDvZOrcwKeWtyYw38pa5 l0qWOi0883wdwy7Riy9+TDr94/ijM+JvvsZK7P0l+OsC877ouFlOE0317lTYJ1g5Ts3yYlNM vBuny/k7gMnXqPllj8FGjbj9y0LfLtnVw9nD5BpU8fVctfjPe1XPTPSnNT9wf7tOiaU4I9FQ i7moOBEA0VVPs/oBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQnOdDtkoFC5xxI0SOeyitZZHO+npOb/Xef1IDeKMYQr727t+bbBLCXC2wqlcwPlp6o6Z+Ha Define additional registers for clock control in Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- arch/arm/include/asm/arch-exynos/clock.h | 36 +++++++++++++++++++++-------- 1 files changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 50da958..7cc3d5e 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -272,7 +272,7 @@ struct exynos5_clock { unsigned int clkout_cmu_cpu; unsigned int clkout_cmu_cpu_div_stat; unsigned char res8[0x5f8]; - unsigned int armclk_stopctrl; + unsigned int armclk_stopctrl; /* base + 0x1000 */ unsigned int atclk_stopctrl; unsigned char res9[0x8]; unsigned int parityfail_status; @@ -323,10 +323,12 @@ struct exynos5_clock { unsigned char res19[0xf8]; unsigned int div_core0; unsigned int div_core1; - unsigned char res20[0xf8]; + unsigned int div_sysrgt; + unsigned char res20[0xf4]; unsigned int div_stat_core0; unsigned int div_stat_core1; - unsigned char res21[0x2f8]; + unsigned int div_stat_sysrgt; + unsigned char res21[0x2f4]; unsigned int gate_ip_core; unsigned char res22[0xfc]; unsigned int clkout_cmu_core; @@ -352,7 +354,11 @@ struct exynos5_clock { unsigned int div_stat_acp; unsigned char res30[0x1fc]; unsigned int gate_ip_acp; - unsigned char res31[0x1fc]; + unsigned char res31a[0xfc]; + unsigned int div_syslft; + unsigned char res31b[0xc]; + unsigned int div_stat_syslft; + unsigned char res31c[0xec]; unsigned int clkout_cmu_acp; unsigned int clkout_cmu_acp_div_stat; unsigned char res32[0x38f8]; @@ -379,7 +385,9 @@ struct exynos5_clock { unsigned int epll_lock; unsigned char res40[0xc]; unsigned int vpll_lock; - unsigned char res41[0xdc]; + unsigned char res41a[0xc]; + unsigned int gpll_lock; + unsigned char res41b[0xcc]; unsigned int cpll_con0; unsigned int cpll_con1; unsigned char res42[0x8]; @@ -390,7 +398,10 @@ struct exynos5_clock { unsigned int vpll_con0; unsigned int vpll_con1; unsigned int vpll_con2; - unsigned char res44[0xc4]; + unsigned char res44a[0x4]; + unsigned int gpll_con0; + unsigned int gpll_con1; + unsigned char res44b[0xb8]; unsigned int src_top0; unsigned int src_top1; unsigned int src_top2; @@ -521,7 +532,9 @@ struct exynos5_clock { unsigned int clkout_cmu_top_div_stat; unsigned char res84[0x37f8]; unsigned int src_lex; - unsigned char res85[0x2fc]; + unsigned char res85[0x1fc]; + unsigned int mux_stat_lex; + unsigned char res85b[0xfc]; unsigned int div_lex; unsigned char res86[0xfc]; unsigned int div_stat_lex; @@ -549,7 +562,8 @@ struct exynos5_clock { unsigned int clkout_cmu_r1x; unsigned int clkout_cmu_r1x_div_stat; unsigned char res98[0x3608]; - unsigned int bpll_lock; + + unsigned int bpll_lock; /* base + 0x2000c */ unsigned char res99[0xfc]; unsigned int bpll_con0; unsigned int bpll_con1; @@ -574,8 +588,10 @@ struct exynos5_clock { unsigned int clkout_cmu_cdrex_div_stat; unsigned char res108[0x8]; unsigned int lpddr3phy_ctrl; - unsigned char res109[0xf5f8]; + unsigned char res109a[0xc]; + unsigned int lpddr3phy_con3; + unsigned int pll_div2_sel; + unsigned char res109b[0xf5e4]; }; #endif - #endif