From patchwork Tue Jun 19 06:45:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9430 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0230F23F28 for ; Tue, 19 Jun 2012 06:41:02 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id B864DA189D3 for ; Tue, 19 Jun 2012 06:41:01 +0000 (UTC) Received: by mail-gh0-f180.google.com with SMTP id z12so4725214ghb.11 for ; Mon, 18 Jun 2012 23:41:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=eIA0FRLuyh3Qs7FST2pTfQG13waYPB3utnj3gY9F+pM=; b=b9t1MTzJ0xNS7db2WpT39kHFRYOZPT1n4lNir6Il62flC38GgGziJlMi0e/3zbPezA Rk3rdfS8AWDbTdPV5DAFcLS704vuvfitvH0/8qmHpX16MQiHEg77PFNGiAu40DFKwsuE /ybc1/GRSRG7o+UDu/f6Ndv8UYxVP2oYZwo2MkjrjOwkjU176ds1/2EOkGydwpn0yODj +ii8w45mc5jh9ZIfY4LhMyAMbcmszpwYiCxprKvuqJ4aYjGpG+Wy0aW7KAZ++FqdRNSG qWRjA/pTosgAhsH5G2qP6dWt13VRHd/0IOdtNZ+/9UtKjqJEkxEsPZy9B51yK+zZzD2e 1dAQ== Received: by 10.50.57.167 with SMTP id j7mr124086igq.53.1340088061332; Mon, 18 Jun 2012 23:41:01 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp109102ibb; Mon, 18 Jun 2012 23:41:00 -0700 (PDT) Received: by 10.68.238.232 with SMTP id vn8mr60694472pbc.78.1340088060570; Mon, 18 Jun 2012 23:41:00 -0700 (PDT) Received: from mailout3.samsung.com (mailout3.samsung.com. [203.254.224.33]) by mx.google.com with ESMTP id ic5si28430769pbc.57.2012.06.18.23.41.00; Mon, 18 Jun 2012 23:41:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5U00B9GQHLA350@mailout3.samsung.com>; Tue, 19 Jun 2012 15:40:59 +0900 (KST) X-AuditID: cbfee61b-b7fcc6d000003a7a-c0-4fe01efab90f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 82.91.14970.AFE10EF4; Tue, 19 Jun 2012 15:40:59 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5U00BUEQJL3P50@mmp2.samsung.com>; Tue, 19 Jun 2012 15:40:58 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com Subject: [PATCH 3/8 V3] EXYNOS: PINMUX: Add pinmux support for I2C Date: Tue, 19 Jun 2012 12:15:14 +0530 Message-id: <1340088319-10072-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340088319-10072-1-git-send-email-rajeshwari.s@samsung.com> References: <1340088319-10072-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMJMWRmVeSWpSXmKPExsVy+t9jQd3fcg/8DXqTLB6uv8liMeXwFxYH Jo871/awBTBGcdmkpOZklqUW6dslcGUsvCRfcEWiomH/G7YGxgciXYycHBICJhIzlr5mgrDF JC7cW8/WxcjFISQwnVFi6o2PjCAJIYGJTBJTNgqB2GwCRhJbT04Di4sISEj86r8KZjMLTGGU 2LU6tIuRg0NYwEnicLcXiMkioCrRN00OpIJXwEOisWcZI8QqBYljU7+ygticAp4Smz4sZILY 5CGx58V59gmMvAsYGVYxiqYWJBcUJ6XnGukVJ+YWl+al6yXn525iBHv9mfQOxlUNFocYBTgY lXh4MyQe+AuxJpYVV+YeYpTgYFYS4V31/76/EG9KYmVValF+fFFpTmrxIUZpDhYlcd4m6wv+ QgLpiSWp2ampBalFMFkmDk6pBsY4ec/X75sPdYlb3doV/Vngsxzvp/1XNPkeT9+z7vzrX/rb PC6p3OE592OK9ym7zH3fHS3ub+pSsj1WvScsLnHNng1sXyQlkw3OTHfVDGN1mcCcOHfa5y2/ neco/Jl5zWTenZ4vef/eV8cnKYpeZfY+Vr39mM+tFwHBnTa/khQ2mR6VcDcSfGupxFKckWio xVxUnAgAdi1B+/YBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQnMMwUHJ4QZgOXL6ov4Sx/Erczj9rDxmt581Cg0LODO+hxcSyEDKtJtgpLlHn1b90mYHBmi This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - Aligned the pinmux functionality as per the latest comments. Changes in V3: - None arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 8 ++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..d28f055 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -184,6 +184,48 @@ static void exynos5_sromc_config(int flags) } } +static void exynos5_i2c_config(int peripheral, int flags) +{ + + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -201,6 +243,16 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SROMC: exynos5_sromc_config(flags); break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos5_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..b861d7d 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,