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[203.254.224.24]) by mx.google.com with ESMTP id ss6si31348119pbc.123.2012.06.18.23.40.55; Mon, 18 Jun 2012 23:40:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5U00BUWQJUUXQ0@mailout1.samsung.com>; Tue, 19 Jun 2012 15:40:53 +0900 (KST) X-AuditID: cbfee61b-b7fcc6d000003a7a-ac-4fe01ef59742 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 9D.81.14970.5FE10EF4; Tue, 19 Jun 2012 15:40:53 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5U00BUEQJL3P50@mmp2.samsung.com>; Tue, 19 Jun 2012 15:40:53 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com Subject: [PATCH 1/8 V3] EXYNOS: CLK: Add i2c clock Date: Tue, 19 Jun 2012 12:15:12 +0530 Message-id: <1340088319-10072-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340088319-10072-1-git-send-email-rajeshwari.s@samsung.com> References: <1340088319-10072-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jQd2vcg/8De78NbR4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CV0dZ2nKngolDF8oexDYyb+LsYOTkkBEwklk45xwRh i0lcuLeerYuRi0NIYDqjxI62l8wQzkQmiXXvmsCq2ASMJLaenMYIYosISEj86r8KZjMLTGGU 2LU6FMQWBqo5NG8PWJxFQFVi7ZUPzCA2r4CHRO+xh1DbFCSOTf3KCmJzCnhKbPqwECwuBFSz 58V59gmMvAsYGVYxiqYWJBcUJ6XnGukVJ+YWl+al6yXn525iBHv/mfQOxlUNFocYBTgYlXh4 MyQe+AuxJpYVV+YeYpTgYFYS4V31/76/EG9KYmVValF+fFFpTmrxIUZpDhYlcd4m6wv+QgLp iSWp2ampBalFMFkmDk6pBsbQUy0SR9sSzjk1r57Esn71qg/R3dcbr1Zwqh0y/sXA8veAkeC5 ZB/R1NwdHc+/Oz8uiCn1VPf99HSWzAn38C9iDtZnqwy6pKvfpW65/1nnhjiXRJJe3btmhzz7 25PSz2m36v5iy43tizaNqikUvt6h3W0eM1tErmGb5sWjO6/dUVdSMc7VVGIpzkg01GIuKk4E AFDOQW/6AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQl9KvfS6Q8CriQynddkk3Txo8V2mMn3MZrRdmIY1E/INEfE++3RuhxWFwe/uOnz58gERDdI This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- changes in V2: - Incorporated comments from Simon Glass which are removed extra braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for return statement. Changes in V3: - None arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..a80928b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = (readl(&clk->div_top1)) >> 24; + ratio &= (0x7); + aclk_66_pre = sclk/(ratio+1); + ratio = readl(&clk->div_top0); + ratio &= (0x7); + aclk_66 = aclk_66_pre/(ratio+1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..72dc655 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -30,6 +30,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);