From patchwork Mon Jun 18 16:35:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 9407 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E7DB323EB4 for ; Mon, 18 Jun 2012 16:36:03 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id B7AEFA184A6 for ; Mon, 18 Jun 2012 16:36:03 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so4171878ggn.11 for ; Mon, 18 Jun 2012 09:36:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Dq2yTER/XsOpraPteZb293fiDZRXMfYzHZiS7aU15J8=; b=Bm32ExClaeWOOUxfhswGvjW2eJt7Nzk71DStpajzMOL3fH3TmqOijFbeUP84vfAUxn dVB2kTvrqcryfkPB66DoqBL/SY7mH4EJg/EvTJiG7MCMeBcO1VsGfHxoQqhwnsfILWIJ hQDRU3k16y1faXIQ66fz3gvZJnhEQu3NZTMwordBKWfy01iqBgiALK3gkJc2f13VTIox uD6rKkUsidWkGmRRRv/u4GoQfjU5y0ty13FJXhMeUz/nHIVZIVUb7w/ySNhy+MhnxX1z GEP5nLptaL2yvYq7Cq6LXh0/NOaVU2CsOQ376vWpl4kb3xc0ffKo8d0Ik4T6rsOBVkDA ZcLQ== Received: by 10.50.46.232 with SMTP id y8mr9021040igm.57.1340037363313; Mon, 18 Jun 2012 09:36:03 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp77799ibb; Mon, 18 Jun 2012 09:36:02 -0700 (PDT) Received: by 10.68.220.39 with SMTP id pt7mr54156501pbc.40.1340037362512; Mon, 18 Jun 2012 09:36:02 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id rn8si20526361pbc.337.2012.06.18.09.36.02 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:36:02 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) smtp.mail=mathieu.poirier@linaro.org Received: by mail-pb0-f50.google.com with SMTP id rr4so9735028pbb.37 for ; Mon, 18 Jun 2012 09:36:02 -0700 (PDT) Received: by 10.68.202.130 with SMTP id ki2mr53865357pbc.52.1340037362256; Mon, 18 Jun 2012 09:36:02 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id os9sm24389049pbb.62.2012.06.18.09.36.00 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:36:01 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Cc: patches@linaro.org, mathieu.poirier@linaro.org, lee.jones@linaro.org Subject: [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 Date: Mon, 18 Jun 2012 10:35:41 -0600 Message-Id: <1340037344-2497-9-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340037344-2497-1-git-send-email-mathieu.poirier@linaro.org> References: <1340037344-2497-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQkBVMGDF/lNPKIpl0QWd813ehjXMKbfFglzl8TgjiIa4gOBWNsg+APWklqIHf/h05KWp6Wl From: "Mathieu J. Poirier" Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/cpu.c | 89 ++++++++++++++++++++-------- arch/arm/include/asm/arch-u8500/hardware.h | 22 ++++++- board/st-ericsson/snowball/snowball.c | 5 ++ 3 files changed, 88 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 593199c..02bb332 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -36,11 +36,19 @@ #define CPUID_DB8500V2 0x412fc091 #define ASICID_DB8500V11 0x008500A1 -static unsigned int read_asicid(void) +static unsigned int read_asicid(void); + +static inline unsigned int read_cpuid(void) { - unsigned int *address = (void *)U8500_BOOTROM_BASE - + U8500_BOOTROM_ASIC_ID_OFFSET; - return readl(address); + unsigned int val; + + /* Main ID register (MIDR) */ + asm("mrc p15, 0, %0, c0, c0, 0" + : "=r" (val) + : + : "cc"); + + return val; } static int cpu_is_u8500v11(void) @@ -53,6 +61,18 @@ static int cpu_is_u8500v2(void) return read_cpuid() == CPUID_DB8500V2; } +static unsigned int read_asicid(void) +{ + unsigned int *address; + + if (cpu_is_u8500v2()) + address = (void *) U8500_ASIC_ID_LOC_V2; + else + address = (void *) U8500_ASIC_ID_LOC_ED_V1; + + return readl(address); +} + #ifdef CONFIG_ARCH_CPU_INIT /* * SOC specific cpu init @@ -68,22 +88,22 @@ int arch_cpu_init(void) #ifdef CONFIG_MMC -#define LDO_VAUX3_MASK 0x3 -#define LDO_VAUX3_ENABLE 0x1 -#define VAUX3_VOLTAGE_2_9V 0xd - -#define AB8500_REGU_CTRL2 0x4 -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 - int u8500_mmc_power_init(void) { int ret; - int val; + int enable, voltage; + int ab8500_revision; - if (!cpu_is_u8500v11()) + if (!cpu_is_u8500v11() && !cpu_is_u8500v2()) return 0; + /* Get AB8500 revision */ + ret = ab8500_read(AB8500_MISC, AB8500_REV_REG); + if (ret < 0) + goto out; + + ab8500_revision = ret; + /* * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD * card to work. This is done by enabling the regulators in the AB8500 @@ -95,33 +115,50 @@ int u8500_mmc_power_init(void) * Turn off and delay is required to have it work across soft reboots. */ - ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); + /* Turn off (read-modify-write) */ + ret = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG); if (ret < 0) goto out; - val = ret; + enable = ret; /* Turn off */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, - val & ~LDO_VAUX3_MASK); + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, + enable & ~LDO_VAUX3_ENABLE_MASK); if (ret < 0) goto out; udelay(10 * 1000); - /* Set the voltage to 2.9V */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, - VAUX3_VOLTAGE_2_9V); + /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */ + ret = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG); if (ret < 0) goto out; - val = val & ~LDO_VAUX3_MASK; - val = val | LDO_VAUX3_ENABLE; + voltage = ret; + + if (ab8500_revision < 0x20) { + voltage &= ~LDO_VAUX3_SEL_MASK; + voltage |= LDO_VAUX3_SEL_2V9; + } else { + voltage &= ~LDO_VAUX3_V2_SEL_MASK; + voltage |= LDO_VAUX3_V2_SEL_2V91; + } + + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG, voltage); + if (ret < 0) + goto out; /* Turn on the supply */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, val); + enable &= ~LDO_VAUX3_ENABLE_MASK; + enable |= LDO_VAUX3_ENABLE_VAL; + + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, enable); out: return ret; diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h index 8044ac3..ee03419 100644 --- a/arch/arm/include/asm/arch-u8500/hardware.h +++ b/arch/arm/include/asm/arch-u8500/hardware.h @@ -77,11 +77,21 @@ #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) /* Last page of Boot ROM */ -#define U8500_BOOTROM_BASE 0x9001f000 -#define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4 +#define U8500_BOOTROM_BASE 0x90000000 +#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) +#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) /* AB8500 specifics */ + +/* address bank */ +#define AB8500_REGU_CTRL2 0x0004 #define AB8500_MISC 0x0010 + +/* registers */ +#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A +#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 +#define AB8500_REV_REG 0x1080 + #define AB8500_GPIO_SEL2_REG 0x1001 #define AB8500_GPIO_DIR2_REG 0x1011 #define AB8500_GPIO_DIR4_REG 0x1013 @@ -89,4 +99,12 @@ #define AB8500_GPIO_OUT2_REG 0x1021 #define AB8500_GPIO_OUT4_REG 0x1023 +#define LDO_VAUX3_ENABLE_MASK 0x3 +#define LDO_VAUX3_ENABLE_VAL 0x1 +#define LDO_VAUX3_SEL_MASK 0xf +#define LDO_VAUX3_SEL_2V9 0xd +#define LDO_VAUX3_V2_SEL_MASK 0x7 +#define LDO_VAUX3_V2_SEL_2V91 0x7 + + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c index bc95c50..2c01bc1 100644 --- a/board/st-ericsson/snowball/snowball.c +++ b/board/st-ericsson/snowball/snowball.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "db8500_pins.h" @@ -268,5 +269,9 @@ int board_late_init(void) if ((raise_ab8500_gpio16() < 0)) printf("error: cant' raise GPIO16\n"); +#ifdef CONFIG_MMC + u8500_mmc_power_init(); +#endif /* CONFIG_MMC */ + return 0; }