From patchwork Mon Jun 18 16:35:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 9410 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CC65123EB4 for ; Mon, 18 Jun 2012 16:36:07 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 9C829A1877B for ; Mon, 18 Jun 2012 16:36:07 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id q6so4284963yen.11 for ; Mon, 18 Jun 2012 09:36:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=5uybgzWA7nXI9JrclgzCkNVd6N9rM8Jq5RLTA/KJk3A=; b=QhTYsFUyuDOOKEBV25XqyMtCUTs8Z1S9pg62F9wvUmt71wc8U3fGznzAAdDiqBiYoU lWGch3i+hfZ0ZvHcklr6I6sdYWJ3T93Tibg7KiO2MXYpRZZPaqwDpdHi8ZM8fyESNZjQ vIBkSCU1FDpgFA6VbGNeGilahrQxKP92duSjAZbHTcJ1H5vg6y2N+x0pH5yI/oNub2q2 3D/i3tvGOEuQ8Ymyd10o/Y0Q5IEuZrF536JNhruT4YBGs6vkRSRCi8ojxHodjegz6e/W eW0emQgwZ5cqGz9boh5QCu/bY22gLLrVK2OkYwgWkPfwwVctT8G7sJ5FCHpqfMm91pr7 T6Ng== Received: by 10.50.203.39 with SMTP id kn7mr9008509igc.53.1340037367007; Mon, 18 Jun 2012 09:36:07 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp77808ibb; Mon, 18 Jun 2012 09:36:06 -0700 (PDT) Received: by 10.68.202.99 with SMTP id kh3mr52624521pbc.157.1340037366322; Mon, 18 Jun 2012 09:36:06 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id rn8si20526361pbc.337.2012.06.18.09.36.06 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:36:06 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) smtp.mail=mathieu.poirier@linaro.org Received: by mail-pb0-f50.google.com with SMTP id rr4so9735028pbb.37 for ; Mon, 18 Jun 2012 09:36:06 -0700 (PDT) Received: by 10.68.194.6 with SMTP id hs6mr54477748pbc.133.1340037366093; Mon, 18 Jun 2012 09:36:06 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id os9sm24389049pbb.62.2012.06.18.09.36.05 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:36:05 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Cc: patches@linaro.org, mathieu.poirier@linaro.org, lee.jones@linaro.org Subject: [PATCH 11/11] snowball: Adding board specific cache cleanup routine Date: Mon, 18 Jun 2012 10:35:44 -0600 Message-Id: <1340037344-2497-12-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340037344-2497-1-git-send-email-mathieu.poirier@linaro.org> References: <1340037344-2497-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQkIYkuFemNKLVeFHD+UqDCzIgOX0PWJiOD8oeb9p3emfSAC3r9Ys/Weib8o6BnqbbuGWTRw From: "Mathieu J. Poirier" This is mandatory in order to boot the Linux kernel. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/cpu.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 02bb332..66a9d2c 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -73,6 +73,15 @@ static unsigned int read_asicid(void) return readl(address); } +void cpu_cache_management(void) +{ + if (cpu_is_u8500v2()) { + *((volatile unsigned int *)(0xA04127CC)) = 0xFF; + *((volatile unsigned int *)(0xA0412900)) = 0xFF; + *((volatile unsigned int *)(0xA0412904)) = 0xFF; + } +} + #ifdef CONFIG_ARCH_CPU_INIT /* * SOC specific cpu init