From patchwork Mon Jun 18 16:25:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 9392 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C7D4123EB4 for ; Mon, 18 Jun 2012 16:25:50 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 967D8A186EF for ; Mon, 18 Jun 2012 16:25:50 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so4301117yhp.11 for ; Mon, 18 Jun 2012 09:25:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=I9by1XGeOi/3BXMo5KEBCWer0XQOm8/LZaleu9U1Cdo=; b=Sa0vvRezW0u9qDlUWxUIjaSks32MZq1qMj6nRZBtoiUqmuyPzImlFDiVg4gcPZttbS BRYF2P0RhBCSAwYS3K2J2Ba1NMbqnwFF9maetqlv0pWEPgXmDNdGUC0kAG/9CHvyKACN 7SVqahCjw0fOjat2fsItdNmdPw8KaQOZDu4q+BkbuhOVbwJsVBC7qnbQtFfTX9DJAN2h 4IrAISZBg8cEC65mAsTrf1yPQWBxQfmEXLiYHFGVwEY09sB6UUA6PMVtNk6tZnhp3VYZ B4GApg9mdhWO0TfV1abEAFvQgYSY/V71b2gQgCvC4grKyOKB11v3/MXiV80eMkdG4uBY XNTQ== Received: by 10.50.57.167 with SMTP id j7mr8967504igq.53.1340036749976; Mon, 18 Jun 2012 09:25:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp77273ibb; Mon, 18 Jun 2012 09:25:49 -0700 (PDT) Received: by 10.68.193.195 with SMTP id hq3mr52724054pbc.30.1340036748801; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) Received: from mail-pb0-f50.google.com (mail-pb0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id qt7si28679973pbc.309.2012.06.18.09.25.48 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:25:48 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) smtp.mail=mathieu.poirier@linaro.org Received: by mail-pb0-f50.google.com with SMTP id rr4so9722167pbb.37 for ; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) Received: by 10.68.231.229 with SMTP id tj5mr33749924pbc.39.1340036748579; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id mq8sm51844pbb.64.2012.06.18.09.25.47 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:25:48 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Cc: patches@linaro.org, mathieu.poirier@linaro.org, lee.jones@linaro.org Subject: [PATCH 04/11] snowball: Adding CPU clock initialisation Date: Mon, 18 Jun 2012 10:25:29 -0600 Message-Id: <1340036736-2436-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> References: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQmxbCLjvfU1/Zn7z7MQGNHQteEbwHKuMXky+XhDuREZ38qZEdJsPM2cYwraqBK9zqaMzHUA From: "Mathieu J. Poirier" Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/clock.c | 34 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/u8500/cpu.c | 2 + arch/arm/include/asm/arch-u8500/clock.h | 5 +--- 3 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c index 9e3b873..fcfd61a 100644 --- a/arch/arm/cpu/armv7/u8500/clock.c +++ b/arch/arm/cpu/armv7/u8500/clock.c @@ -54,3 +54,37 @@ void u8500_clock_enable(int periph, int cluster, int kern) if (cluster != -1) writel(1 << cluster, &clkrst->pcken); } + +void db8500_clocks_init(void) +{ + /* + * Enable all clocks. This is u-boot, we can enable it all. There is no + * powersave in u-boot. + */ + + u8500_clock_enable(1, 9, -1); /* GPIO0 */ + u8500_clock_enable(2, 11, -1);/* GPIO1 */ + u8500_clock_enable(3, 8, -1); /* GPIO2 */ + u8500_clock_enable(5, 1, -1); /* GPIO3 */ + u8500_clock_enable(3, 6, 6); /* UART2 */ + u8500_clock_enable(3, 3, 3); /* I2C0 */ + u8500_clock_enable(1, 5, 5); /* SDI0 */ + u8500_clock_enable(2, 4, 2); /* SDI4 */ + u8500_clock_enable(6, 6, -1); /* MTU0 */ + u8500_clock_enable(3, 4, 4); /* SDI2 */ + + /* + * Enabling clocks for all devices which are AMBA devices in the + * kernel. Otherwise they will not get probe()'d because the + * peripheral ID register will not be powered. + */ + + /* XXX: some of these differ between ED/V1 */ + + u8500_clock_enable(1, 1, 1); /* UART1 */ + u8500_clock_enable(1, 0, 0); /* UART0 */ + u8500_clock_enable(3, 2, 2); /* SSP1 */ + u8500_clock_enable(3, 1, 1); /* SSP0 */ + u8500_clock_enable(2, 8, -1); /* SPI0 */ + u8500_clock_enable(2, 5, 3); /* MSP2 */ +} diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 04f4b19..fece201 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_ARCH_CPU_INIT /* @@ -35,6 +36,7 @@ int arch_cpu_init(void) { db8500_prcmu_init(); + db8500_clocks_init(); return 0; } diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h index b00ab0d..2a14784 100644 --- a/arch/arm/include/asm/arch-u8500/clock.h +++ b/arch/arm/include/asm/arch-u8500/clock.h @@ -64,9 +64,6 @@ struct prcmu { extern void u8500_clock_enable(int periph, int kern, int cluster); -static inline void u8500_prcmu_enable(unsigned int *reg) -{ - writel(readl(reg) | (1 << 8), reg); -} +void db8500_clocks_init(void); #endif /* __ASM_ARCH_CLOCK */