From patchwork Mon Jun 18 16:25:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 9391 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8A06223F28 for ; Mon, 18 Jun 2012 16:25:49 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4DEEDA184F3 for ; Mon, 18 Jun 2012 16:25:49 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id q6so4272800yen.11 for ; Mon, 18 Jun 2012 09:25:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=99mlWH4wXxtPXe+G1pYUqMkhqdc/jNnpw04bDZ95tGk=; b=Zn1YYOeRvXUQAtHizy35FCDbSriPGzFPBHuTZq9SoIJP2/WsLx/IcuWju6rFH5UAdl p9K7fDDlW9vgHaA66dxFCLBukS6c/5SsVHRrFqviXIq9fElROQuP4z7Lx56BGNMUgUkD 9WQ2iHWg4wNpqthzgMdn1UeKEVkgKDXgvc0U7RAetJ/Panica97EQOWC9j6//IVwFv4d +VRonUWR9JJ8k+jWNVYcV9cCd3ysZpOFoR6qJzfgOIn+zLRYhisvztGFwmvZ4iDssbhA m2a3Rqdfec6lbhkb8NfAa/t8f3XL5GgAzrHjAP0e0mGSifWf4qJhhwVTdOQP233nr3Ob XLLw== Received: by 10.42.210.193 with SMTP id gl1mr5543639icb.57.1340036748862; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp77269ibb; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) Received: by 10.68.226.226 with SMTP id rv2mr53599062pbc.101.1340036747783; Mon, 18 Jun 2012 09:25:47 -0700 (PDT) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id gk9si25764445pbc.338.2012.06.18.09.25.47 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:25:47 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) smtp.mail=mathieu.poirier@linaro.org Received: by mail-pz0-f50.google.com with SMTP id h15so8066502dan.37 for ; Mon, 18 Jun 2012 09:25:47 -0700 (PDT) Received: by 10.68.242.7 with SMTP id wm7mr53453410pbc.98.1340036747461; Mon, 18 Jun 2012 09:25:47 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id mq8sm51844pbb.64.2012.06.18.09.25.46 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:25:46 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Cc: patches@linaro.org, mathieu.poirier@linaro.org, lee.jones@linaro.org Subject: [PATCH 03/11] snowball: Adding architecture dependent initialisation Date: Mon, 18 Jun 2012 10:25:28 -0600 Message-Id: <1340036736-2436-4-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> References: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQm1T+l3tm0nwhqEPHvpHlYDh/IQfz+O5Uekm6gzKeglaXHcwNZYdrw4TwOUHi5IHAAr3mMM From: "Mathieu J. Poirier" Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/Makefile | 2 +- arch/arm/cpu/armv7/u8500/cpu.c | 41 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/u8500/prcmu.c | 30 ++++++++++++++++++++++ arch/arm/include/asm/arch-u8500/prcmu.h | 24 ++++++++++++++---- board/st-ericsson/u8500/u8500_href.c | 2 +- include/configs/snowball.h | 1 + 6 files changed, 93 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile index 77accde..ce8af96 100644 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ b/arch/arm/cpu/armv7/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = timer.o clock.o prcmu.o +COBJS = timer.o clock.o prcmu.o cpu.o SOBJS = lowlevel.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c new file mode 100644 index 0000000..04f4b19 --- /dev/null +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2012 Linaro Limited + * Mathieu Poirier + * + * Based on original code from Joakim Axelsson at ST-Ericsson + * (C) Copyright 2010 ST-Ericsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_ARCH_CPU_INIT +/* + * SOC specific cpu init + */ +int arch_cpu_init(void) +{ + db8500_prcmu_init(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c index 119ead3..6187dcc 100644 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -40,6 +40,8 @@ #define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) #define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) +#define I2C_MBOX_BIT (1 << 5) + static int prcmu_is_ready(void) { int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; @@ -162,3 +164,31 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) return -1; } } + +void u8500_prcmu_enable(u32 *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +void db8500_prcmu_init(void) +{ + /* Enable timers */ + writel(1 << 17, PRCM_TCR); + + u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); + /* PER4CLK does not exist */ + u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); + /* Only exists in ED but is always ok to write to */ + u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); + + /* Clean up the mailbox interrupts after pre-u-boot code. */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); +} diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 0836983..1fd4d2a 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -27,12 +27,23 @@ #define I2C_RD_OK 2 #define I2CWRITE 0 -#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE -#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ - -#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ -#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ +#define PRCMU_BASE U8500_PRCMU_BASE +#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) +#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) +#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) +#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) +#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) +#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) +#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) +#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) +#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) +#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) +#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) +#define PRCM_TCR (PRCMU_BASE + 0x1C8) +#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44) +#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4) +#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC) /* Mailbox 5 Requests */ #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) @@ -52,4 +63,7 @@ extern int prcmu_i2c_read(u8 reg, u16 slave); extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); +void u8500_prcmu_enable(u32 *reg); +void db8500_prcmu_init(void); + #endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index 6e3fc87..fe72684 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -26,8 +26,8 @@ #include #include #include -#ifdef CONFIG_MMC #include +#ifdef CONFIG_MMC #include "../../../drivers/mmc/arm_pl180_mmci.h" #endif diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 845db29..f959417 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -31,6 +31,7 @@ #define CONFIG_SNOWBALL 1 #define CONFIG_SYS_ICACHE_OFF 1 #define CONFIG_SYS_DCACHE_OFF 1 +#define CONFIG_ARCH_CPU_INIT 1 /* * High Level Configuration Options