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[203.254.224.34]) by mx.google.com with ESMTP id ru5si5530113pbc.341.2012.05.25.04.51.54; Fri, 25 May 2012 04:51:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4K001ZWUA7SXN0@mailout4.samsung.com>; Fri, 25 May 2012 20:51:53 +0900 (KST) X-AuditID: cbfee61b-b7faf6d000001f49-6e-4fbf7259c03f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 29.C5.08009.9527FBF4; Fri, 25 May 2012 20:51:53 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M4K00LCRU6DUZ50@mmp1.samsung.com>; Fri, 25 May 2012 20:51:53 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, tlambert@chromium.org Subject: [PATCH 2/4] EXYNOS5: PINMUX: Add pinmux for SDMMC4 Date: Fri, 25 May 2012 17:23:16 +0530 Message-id: <1337946798-1660-3-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> References: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jAd3Iov3+Biu75Swerr/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlXDr/hbXgmUjFxY8L2BoY7wl0MXJySAiYSHyZ9YQR whaTuHBvPVsXIxeHkMAiRomTi+eyQDgTmSQ+3WpkBqliEzCS2HpyGliHiICExK/+q4wgRcwC 7YwSXdsugRUJC1hL3Oj4yAJiswioSqy58gysgVfAXWL5in5WiHUKEsemfgWzOQU8JG4uWcYE YgsB1Wz5u4p1AiPvAkaGVYyiqQXJBcVJ6blGesWJucWleel6yfm5mxjBAfBMegfjqgaLQ4wC HIxKPLyVUfv9hVgTy4orcw8xSnAwK4nwsqQBhXhTEiurUovy44tKc1KLDzFKc7AoifM+WbLD X0ggPbEkNTs1tSC1CCbLxMEp1cAYbFkU/kbiYPatK3vNAr5pab05IP9ewmH+9TMC4Uyfjnxj PaN5woejW1By29rVlV4ulfsvNGzJj7ZRyFk593mWRMb+7UE9HZMmePkqeC5Q52tYsP9jsHGu b9WjG5t0Lpj+mS4mKbJ23e8teWXsHAXqCxe02Yaun8RtMrWmKmCpftR9pTLdxTVKLMUZiYZa zEXFiQCVtCW//AEAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkPNfzoQ4/UCU7w6PtmgjlAuXLst1SOVFD2m7PnCwYYoUYpV9jmB/deZnfQD84RCdjjwuxM Add pinmux support for SDMMC4 on EXYNOS5. Signed-off-by: Terry Lambert Signed-off-by: Rajeshwari Shinde --- This patch is based on: "EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 103bcbb..9319fd6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i, start, count; + int i, start, count, pin, pin_ext, drv; switch (peripheral) { case PERIPH_ID_UART0: @@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + pin = GPIO_FUNC(0x2); + pin_ext = GPIO_FUNC(0x3); + drv = GPIO_DRV_4X; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; @@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break; + case PERIPH_ID_SDMMC4: + bank = &gpio1->c0; bank_ext = &gpio1->c1; + pin = GPIO_FUNC(0x3); + pin_ext = GPIO_FUNC(0x4); + drv = GPIO_DRV_2X; + break; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags) } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(bank_ext, i, pin_ext); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank_ext, i, drv); } } for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank, i, drv); } for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank, i, drv); } break; case PERIPH_ID_SROMC: