From patchwork Fri May 18 12:12:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 8810 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7525223E49 for ; Fri, 18 May 2012 12:12:37 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 2FB26A18043 for ; Fri, 18 May 2012 12:12:37 +0000 (UTC) Received: by yenq6 with SMTP id q6so3309031yen.11 for ; Fri, 18 May 2012 05:12:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=l5D0kwupYWe4UJ9FmuWTnD3fOVCGo3Gjbt531fq3A6w=; b=KogUfExqY/vQPoDSPFhaS+vBp3ptQLixCRqow5M7NencjZRJOF31F/3SZO8CMr6Kg1 hBzmBYPlkb73+VwsX5lONngNKUJYGAg/6ixN05SVSqxYjwwTEGnx9Rpcl0wVzYklGKVN RD80aK6/OYqFpJhOXGPeSCDzOLom8zAP+xN0mtZSYscOoJ1aXpOlNVYaA0jbJipnIAgG mONhmRY5+GqbI7mocSpNB7hJPTW0RiSuhVS+zZEe+28u+zs//B/Ds+CCGwqTCD4C/hZ4 E1YoVI3sG+kJ7FBtfOpvaRJg7LNkc29P7ccspIjeZELYyuTFxwcE9hmM6V7zOtLgyslG QQ6g== Received: by 10.50.87.227 with SMTP id bb3mr234456igb.57.1337343156352; Fri, 18 May 2012 05:12:36 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp100098ibd; Fri, 18 May 2012 05:12:35 -0700 (PDT) Received: by 10.68.217.100 with SMTP id ox4mr38180247pbc.87.1337343155179; Fri, 18 May 2012 05:12:35 -0700 (PDT) Received: from mailout4.samsung.com (mailout4.samsung.com. [203.254.224.34]) by mx.google.com with ESMTP id hz10si15596916pbc.73.2012.05.18.05.12.34; Fri, 18 May 2012 05:12:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4700056WKYRL10@mailout4.samsung.com>; Fri, 18 May 2012 21:12:34 +0900 (KST) X-AuditID: cbfee61a-b7be0ae000001293-bb-4fb63cb1bdee Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (MMPCPMTA) with SMTP id BA.6D.04755.1BC36BF4; Fri, 18 May 2012 21:12:34 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M470045KWF74W10@mmp2.samsung.com>; Fri, 18 May 2012 21:12:33 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, clchiou@chromium.org, waihong@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, dianders@chromium.org, plagnioj@jcrosoft.com Subject: [PATCH 3/8] EXYNOS: PINMUX: Add pinmux support for I2C Date: Fri, 18 May 2012 17:42:28 +0530 Message-id: <1337343153-3019-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1337343153-3019-1-git-send-email-rajeshwari.s@samsung.com> References: <1337343153-3019-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQnmc5InriI3VTXC9RVg9hCvbbAUagYls3gDpEXCn/OnnXDB0Vzse9WLSXehK2nB7dtc587d This patch adds pinmux code for I2C. Signed-off-by: Leela Krishna Amudala Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- This patch depends on the following patch: "[U-Boot] [PATCH 1/2] exynos5: pinmux: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 32 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/pinmux.h | 8 +++++++ 2 files changed, 40 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 11f4b71..103bcbb 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -170,6 +170,38 @@ int exynos5_pinmux_config(int peripheral, int flags) s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); } break; + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h index 306f521..b3b7f80 100644 --- a/arch/arm/include/asm/arch-exynos/pinmux.h +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,