From patchwork Tue May 8 10:12:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 8461 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5B90F23E23 for ; Tue, 8 May 2012 10:10:49 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 2B6FFA187E4 for ; Tue, 8 May 2012 10:10:49 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so1244181yhp.11 for ; Tue, 08 May 2012 03:10:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=LajAqr5mYaEa3DVU8cLOYc0d/32NNlg89ROdNTM28d0=; b=QtGpR/a60QJebWHOV/qBoGf8cXFM/JVcVKSVmaY3m1xteNtav7otxb++QYz3+rTWy4 JMfzDcJv2GHARDTe725qHlrJsucjyM4SN9Zsk94Ji+xkz1KhsMJuaEOQWexlN7VkkTh4 E23UkNKvt0e8oxsZU1feScwGspIL3x+8GomJJNNUaNkTWuIWgrNbcrXvTrAU2OfuPlYl 7Z/V9n5AzjvcNm+dd1Z6qMjTM9F6/nBbcvPfFJjpG645+HzPbn2F6qLwwtaQe9S5tPEL ekSeXK5ZHLmxWhhsUyZ1KLLTJgOtNRnI+m6YQUM3gNmOJka2j0ZW6oyWCaNVwRJHWkBX Me+w== Received: by 10.42.122.76 with SMTP id m12mr1565545icr.38.1336471848654; Tue, 08 May 2012 03:10:48 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.73.147 with SMTP id q19csp188747ibj; Tue, 8 May 2012 03:10:48 -0700 (PDT) Received: by 10.68.216.98 with SMTP id op2mr4943800pbc.93.1336471847965; Tue, 08 May 2012 03:10:47 -0700 (PDT) Received: from mailout4.samsung.com (mailout4.samsung.com. [203.254.224.34]) by mx.google.com with ESMTP id jo6si1834308pbc.249.2012.05.08.03.10.47; Tue, 08 May 2012 03:10:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M3P008GA89Y7DD0@mailout4.samsung.com> for patches@linaro.org; Tue, 08 May 2012 19:10:46 +0900 (KST) X-AuditID: cbfee61b-b7c60ae000000c58-38-4fa8f126d247 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id C3.66.03160.621F8AF4; Tue, 08 May 2012 19:10:46 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M3P002KH87WVYL0@mmp2.samsung.com> for patches@linaro.org; Tue, 08 May 2012 19:10:46 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, marex@denx.de, l.majewski@samsung.com, sjg@chromium.org, clchiou@chromium.org, waihong@chromium.org, mk7.kang@samsung.com, k.chander@samsung.com, gautam.vivek@samsung.com Subject: [PATCH 4/6 V3] EXYNOS: Add power Enable/Disable for USB-EHCI Date: Tue, 08 May 2012 15:42:00 +0530 Message-id: <1336471922-19336-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1336471922-19336-1-git-send-email-rajeshwari.s@samsung.com> References: <1336471922-19336-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQlqdIguPfoSdddJqrBB3RHtuHU6IixblgRJ2nZPDKsPyXasdrlvI0eloVBKrxtreyuXlUSt This patch adds functions to enable/disable the power of USB host controller for EXYNOS5. Signed-off-by: Vivek Gautam Signed-off-by: Che-Liang Chiou Signed-off-by: Rajeshwari Shinde --- Chnages in v2: - Removed setting of SYSREG registers and moved to system.c. - Enabling and Disabling of USB_PHY_CTRL was moved to single function. Changes in v3: - Removed function to set PS_HOLD as it was not required for USB. - Renamed power_enable_usb_phy and exynos5_enable_usb_phy to set_usb_phy_ctrl and exynos5_set_usb_phy_ctrl. - Added defination for POWER_USB_HOST_PHY_CTRL_DISABLE. This patch is based on: USB: EXYNOS: Add ehci support.patch arch/arm/cpu/armv7/exynos/power.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 4 ++++ drivers/usb/host/ehci-exynos.c | 5 +++++ 3 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index c765304..e09917f 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) if (cpu_is_exynos4()) exynos4_mipi_phy_control(dev_index, enable); } + +void exynos5_set_usb_phy_ctrl(unsigned int enable) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + +void set_usb_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_set_usb_phy_ctrl(enable); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 4236beb..30aba16 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -855,4 +855,8 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) +void set_usb_phy_ctrl(unsigned int enable); + +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) #endif diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 90d66d3..093b13d 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ehci.h" #include "ehci-core.h" @@ -33,6 +34,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) { set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); + set_usb_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -73,6 +76,8 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + + set_usb_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } /*