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[203.254.224.34]) by mx.google.com with ESMTP id y10si2336069pbg.166.2012.05.03.23.55.29; Thu, 03 May 2012 23:55:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M3H00BV1KJUR770@mailout4.samsung.com> for patches@linaro.org; Fri, 04 May 2012 15:55:28 +0900 (KST) X-AuditID: cbfee61a-b7b97ae000004342-1c-4fa37d60519c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (MMPCPMTA) with SMTP id 21.26.17218.06D73AF4; Fri, 04 May 2012 15:55:28 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M3H00HYCKIU2OC1@mmp2.samsung.com> for patches@linaro.org; Fri, 04 May 2012 15:55:28 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, marex@denx.de, l.majewski@samsung.com, sjg@chromium.org, clchiou@chromium.org, waihong@chromium.org, mk7.kang@samsung.com, k.chander@samsung.com Subject: [PATCH 2/2] exynos: smdk5250: Enable the pinmux setup Date: Fri, 04 May 2012 12:26:37 +0530 Message-id: <1336114597-11852-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1336114597-11852-1-git-send-email-rajeshwari.s@samsung.com> References: <1336114597-11852-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQntFR3Q/fRPVYJJrq9xLctyX4CX0Kja8Gt52EqRP303FWY5Siq+oEcvqO5nZUnyk+KmO9QC Use the pinmux configuration function for SMDK5250. Signed-off-by: Abhilash Kesavan Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/Makefile | 2 +- board/samsung/smdk5250/smdk5250.c | 160 ++++++------------------------------ 2 files changed, 26 insertions(+), 136 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index 90ec2bd..9119961 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o power.o soc.o system.o +COBJS += clock.o power.o soc.o system.o pinmux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 32786e2..4c0398d 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -26,6 +26,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -35,72 +36,7 @@ struct exynos5_gpio_part1 *gpio1; static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - int i; - - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); - - for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); - } + int err; /* Ethernet needs data bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK) @@ -112,6 +48,11 @@ static void smc9115_pre_init(void) | SROMC_BC_PMC(0x01); /* Select and configure the SROMC bank */ + err = exynos_pinmux_config(PERIPH_ID_SROMC, + CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT); + if (err < 0) + debug("SROMC not configured\n"); + s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); } #endif @@ -186,31 +127,12 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPC2[0] SD_2_CLK(2) - * GPC2[1] SD_2_CMD(2) - * GPC2[2] SD_2_CDn - * GPC2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPC2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2)); + int err; - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X); - - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err < 0) { + debug("SDMMC2 not configured\n"); + return err; } err = s5p_mmc_init(2, 4); @@ -220,55 +142,23 @@ int board_mmc_init(bd_t *bis) static void board_uart_init(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - int i; + int err; - /* - * UART0 GPIOs : GPA0CON[3:0] 0x2222 - * Must set CFG17 switches to select UART0 to use. - */ - for (i = 0; i <= 3; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); - } + err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); + if (err < 0) + debug("UART0 not configured\n"); - /* - * UART1 GPIOs : GPA0CON[5:4] 0x22 - * Must set CFG17 switches to select UART1 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); - } + err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); + if (err < 0) + debug("UART1 not configured\n"); - /* - * UART2 GPIOs : GPA1CON[1:0] 0x22 - * Must set CFG17 switches to select UART2 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 0; i <= 1; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); - } - - /* - * UART3 GPIOs : GPA1CON[5:4] 0x22 - * Must set CFG16 switches to select UART3 to use. - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); - } + err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); + if (err < 0) + debug("UART2 not configured\n"); - /* - * There's no mux for UART4--it's internal only - */ + err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + if (err < 0) + debug("UART3 not configured\n"); } #ifdef CONFIG_BOARD_EARLY_INIT_F