From patchwork Wed May 2 13:52:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 8354 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2289A23E42 for ; Wed, 2 May 2012 13:53:12 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id D0110A18440 for ; Wed, 2 May 2012 13:53:11 +0000 (UTC) Received: by ghbz12 with SMTP id z12so847441ghb.11 for ; Wed, 02 May 2012 06:53:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=/zBUbPrOMSyw2VtowXmQ4BlAB9HRuHMQELWhpWTQvfk=; b=oTnC0N/IY4su8BUNu1cqMIOepC+2qhWuVzJVocEX9ezLYSvlnXmJVrT86rC073jZqc 6+4U6Dg2VCxifkO/DQC6Ni5A86QVUvoY6oiXe/XglBXzsAYV98mo0hkXr/OhW61slV3r QumVx6kQ3SZDIOIVU3pltQojl95O5i4vOJU8QsXiVfhYTvksdxAQJP7MXK5UQuJw5KAX MBKWjRZER9Oi+UUOptwoEwxjeD96X9SC80lvFmYqjYg5dEViLdPrHwotNZYXpBddmCdQ VulMBuhuIqfwuKu9eD555mrJEZ2Y24Caxwal9OK2ULB27a/musLrshF+Lcfko9h4+0m+ r28Q== Received: by 10.50.10.225 with SMTP id l1mr5210948igb.1.1335966791078; Wed, 02 May 2012 06:53:11 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp253109ibt; Wed, 2 May 2012 06:53:10 -0700 (PDT) Received: by 10.68.129.131 with SMTP id nw3mr56653741pbb.150.1335966790258; Wed, 02 May 2012 06:53:10 -0700 (PDT) Received: from mailout3.samsung.com (mailout3.samsung.com. [203.254.224.33]) by mx.google.com with ESMTP id s4si1906421pbc.105.2012.05.02.06.53.09; Wed, 02 May 2012 06:53:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M3E00DA6EK434Q0@mailout3.samsung.com> for patches@linaro.org; Wed, 02 May 2012 22:53:09 +0900 (KST) X-AuditID: cbfee61a-b7bfeae0000070f7-51-4fa13c45440e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (MMPCPMTA) with SMTP id F8.F2.28919.54C31AF4; Wed, 02 May 2012 22:53:09 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M3E007JQEG9E710@mmp2.samsung.com> for patches@linaro.org; Wed, 02 May 2012 22:53:09 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, marex@denx.de, l.majewski@samsung.com, sjg@chromium.org, clchiou@chromium.org, waihong@chromium.org, k.chander@samsung.com Subject: [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI Date: Wed, 02 May 2012 19:22:40 +0530 Message-id: <1335966762-9769-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1335966762-9769-1-git-send-email-rajeshwari.s@samsung.com> References: <1335966762-9769-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQki4od2358rjSVT5nSxgy3WQ0733inF+KGZsUCRH7dLvXeQB0exoWk3KOsnXafExZEbVFE8 This patch adds functions to enable/disable the power of USB host controller for exynos5. This patch depends on the patch: USB: S5P: Add ehci support.patch Signed-off-by: Vivek Gautam Signed-off-by: Che-Liang Chiou Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/power.c | 59 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 5 ++ arch/arm/include/asm/arch-exynos/sysreg.h | 1 + drivers/usb/host/ehci-s5p.c | 3 + 4 files changed, 68 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index c765304..a943219 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include static void exynos4_mipi_phy_control(unsigned int dev_index, unsigned int enable) @@ -52,3 +54,60 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) if (cpu_is_exynos4()) exynos4_mipi_phy_control(dev_index, enable); } + +void exynos5_ps_hold_setup(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Set PS-Hold high */ + setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH); +} + +void exynos5_enable_usb_phy(void) +{ + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + unsigned int phy_cfg; + + /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ + phy_cfg = readl(&sysreg->usb20_phy_cfg); + if (phy_cfg & USB20_PHY_CFG_EN) { + debug("USB 2.0 HOST link already selected\n"); + } else { + phy_cfg |= USB20_PHY_CFG_EN; + writel(phy_cfg, &sysreg->usb20_phy_cfg); + } + + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN); +} + +void exynos5_disable_usb_phy(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Disabling USBHost_PHY */ + clrbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN); +} + +void ps_hold_setup(void) +{ + if (cpu_is_exynos5()) + exynos5_ps_hold_setup(); +} + +void power_enable_usb_phy(void) +{ + if (cpu_is_exynos5()) + exynos5_enable_usb_phy(); +} + +void power_disable_usb_phy(void) +{ + if (cpu_is_exynos5()) + exynos5_disable_usb_phy(); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 4236beb..4e2448b 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -855,4 +855,9 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) +void power_enable_usb_phy(void); +void power_disable_usb_phy(void); + #endif diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h index aca4b2b..2d8d35a 100644 --- a/arch/arm/include/asm/arch-exynos/sysreg.h +++ b/arch/arm/include/asm/arch-exynos/sysreg.h @@ -40,4 +40,5 @@ struct exynos5_sysreg { }; #endif +#define USB20_PHY_CFG_EN (1 << 0) #endif diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c index 4dd4ec1..e575c48 100644 --- a/drivers/usb/host/ehci-s5p.c +++ b/drivers/usb/host/ehci-s5p.c @@ -30,6 +30,7 @@ /* Setup the EHCI host controller. */ static void setup_usb_phy(struct s5p_usb_phy *usb) { + power_enable_usb_phy(); clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -70,6 +71,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb) HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + + power_disable_usb_phy(); } /*