From patchwork Wed May 2 13:48:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 8351 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 457EF23E42 for ; Wed, 2 May 2012 13:47:27 +0000 (UTC) Received: from mail-wi0-f176.google.com (mail-wi0-f176.google.com [209.85.212.176]) by fiordland.canonical.com (Postfix) with ESMTP id 367E2A18277 for ; Wed, 2 May 2012 13:47:27 +0000 (UTC) Received: by wibhm17 with SMTP id hm17so4316983wib.17 for ; Wed, 02 May 2012 06:47:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:x-brightmail-tracker :x-tm-as-mml:x-gm-message-state; bh=cI1fMEIsqJz1PVNCrp1E/oUXDzh+OFkxsrlNMyIURoI=; b=PgZac9y4fEZL0ZmH4yDaKtZL+Gi1ia/GX48CdCU6xNV+iVnLLOaVpYG4B6YDIkQGlm tV60XuSEYfNJX8xl/sbQQU0OO/1qy3+2Cxi+fnbFNIwa8M1QcYhVPBWY/okndccAL4PD q1sbympx5uRF3SKQBT9fd4l90111kGei0Mj7XEGWGuY8zEhjTUNUBYgmjOLyAjwY4zrB 191Y2l9J9h7THcfnZJD2/u6q0NqPVKyko7jQp1Ed5Ca0p6MC4Px8PyTUx5AJeM9BXxIB 6knqevYCWMD+hSRIwjaHpmXmMAO6QNQgfaPjnhh3tLJDi6PRjwSxcbb/F/UA08W3IgsT sc5Q== Received: by 10.50.160.225 with SMTP id xn1mr5021679igb.3.1335966446431; Wed, 02 May 2012 06:47:26 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp252689ibt; Wed, 2 May 2012 06:47:25 -0700 (PDT) Received: by 10.68.230.40 with SMTP id sv8mr9784949pbc.124.1335966445335; Wed, 02 May 2012 06:47:25 -0700 (PDT) Received: from mailout3.samsung.com (mailout3.samsung.com. [203.254.224.33]) by mx.google.com with ESMTP id oo6si1823981pbc.127.2012.05.02.06.47.24; Wed, 02 May 2012 06:47:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M3E002XWEAYN6U0@mailout3.samsung.com> for patches@linaro.org; Wed, 02 May 2012 22:47:23 +0900 (KST) X-AuditID: cbfee61b-b7ce2ae00000583e-ba-4fa13aea9333 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id CE.9C.22590.AEA31AF4; Wed, 02 May 2012 22:47:22 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M3E0073EE9UE710@mmp2.samsung.com> for patches@linaro.org; Wed, 02 May 2012 22:47:22 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, marex@denx.de, l.majewski@samsung.com, sjg@chromium.org, clchiou@chromium.org, waihong@chromium.org, k.chander@samsung.com Subject: [PATCH V2] USB: S5P: Add ehci support Date: Wed, 02 May 2012 19:18:51 +0530 Message-id: <1335966531-9701-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQnd+xnektGwAnirtR34fhHy9B1QsIKDP3LbQj03lRNry3ICHdfwf6/hvNxncai/FkJxi6zR This patch adds ehci driver support for s5p. Signed-off-by: Vivek Gautam Signed-off-by: Rajeshwari Shinde --- arch/arm/include/asm/arch-exynos/ehci-s5p.h | 66 ++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-s5p.c | 110 +++++++++++++++++++++++++++ 3 files changed, 177 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/ehci-s5p.h create mode 100644 drivers/usb/host/ehci-s5p.c diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci-s5p.h new file mode 100644 index 0000000..68feb85 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/ehci-s5p.h @@ -0,0 +1,66 @@ +/* + * SAMSUNG S5P USB HOST EHCI Controller + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ +#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ + +#define CLK_24MHZ 5 + +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0) + +#define HOST_CTRL0_FSEL_MASK (7 << 16) + +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26) + +/* Register map for PHY control */ +struct s5p_usb_phy { + unsigned int usbphyctrl0; + unsigned int usbphytune0; + unsigned int reserved1[2]; + unsigned int hsicphyctrl1; + unsigned int hsicphytune1; + unsigned int reserved2[2]; + unsigned int hsicphyctrl2; + unsigned int hsicphytune2; + unsigned int reserved3[2]; + unsigned int ehcictrl; + unsigned int ohcictrl; + unsigned int usbotgsys; + unsigned int reserved4; + unsigned int usbotgtune; +}; + +/* Switch on the VBUS power. */ +int board_usb_vbus_init(void); + +#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 0d4657e..59c3e57 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c new file mode 100644 index 0000000..4dd4ec1 --- /dev/null +++ b/drivers/usb/host/ehci-s5p.c @@ -0,0 +1,110 @@ +/* + * SAMSUNG S5P USB HOST EHCI Controller + * + * Copyright (C) 2012 Samsung Electronics Co.Ltd + * Vivek Gautam + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "ehci.h" +#include "ehci-core.h" + +/* Setup the EHCI host controller. */ +static void setup_usb_phy(struct s5p_usb_phy *usb) +{ + clrbits_le32(&usb->usbphyctrl0, + HOST_CTRL0_FSEL_MASK | + HOST_CTRL0_COMMONON_N | + /* HOST Phy setting */ + HOST_CTRL0_PHYSWRST | + HOST_CTRL0_PHYSWRSTALL | + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESUSPEND | + HOST_CTRL0_FORCESLEEP); + + setbits_le32(&usb->usbphyctrl0, + /* Setting up the ref freq */ + (CLK_24MHZ << 16) | + /* HOST Phy setting */ + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); + udelay(10); + clrbits_le32(&usb->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); + udelay(20); + + /* EHCI Ctrl setting */ + setbits_le32(&usb->ehcictrl, + EHCICTRL_ENAINCRXALIGN | + EHCICTRL_ENAINCR4 | + EHCICTRL_ENAINCR8 | + EHCICTRL_ENAINCR16); +} + +/* Reset the EHCI host controller. */ +static void reset_usb_phy(struct s5p_usb_phy *usb) +{ + /* HOST_PHY reset */ + setbits_le32(&usb->usbphyctrl0, + HOST_CTRL0_PHYSWRST | + HOST_CTRL0_PHYSWRSTALL | + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESUSPEND | + HOST_CTRL0_FORCESLEEP); +} + +/* + * EHCI-initialization + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + struct s5p_usb_phy *usb; + + usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); + setup_usb_phy(usb); + + hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)hccr, (uint32_t)hcor, + (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the EHCI host controller. + */ +int ehci_hcd_stop() +{ + struct s5p_usb_phy *usb; + + usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); + reset_usb_phy(usb); + + return 0; +}