From patchwork Sat Mar 3 20:21:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 7081 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8F05623EAF for ; Sat, 3 Mar 2012 20:21:22 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4FB90A1866A for ; Sat, 3 Mar 2012 20:21:22 +0000 (UTC) Received: by iage36 with SMTP id e36so5181545iag.11 for ; Sat, 03 Mar 2012 12:21:21 -0800 (PST) Received: by 10.50.95.230 with SMTP id dn6mr2102512igb.0.1330806081678; Sat, 03 Mar 2012 12:21:21 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp11962ibg; Sat, 3 Mar 2012 12:21:20 -0800 (PST) Received: by 10.152.134.146 with SMTP id pk18mr10793598lab.43.1330806079479; Sat, 03 Mar 2012 12:21:19 -0800 (PST) Received: from mail.df.lth.se (mail.df.lth.se. [194.47.250.12]) by mx.google.com with ESMTPS id q6si4889002lbe.45.2012.03.03.12.21.18 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 03 Mar 2012 12:21:19 -0800 (PST) Received-SPF: neutral (google.com: 194.47.250.12 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=194.47.250.12; Authentication-Results: mx.google.com; spf=neutral (google.com: 194.47.250.12 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) smtp.mail=linus.walleij@linaro.org Received: from fecusia (c83-249-219-176.bredband.comhem.se [83.249.219.176]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.df.lth.se (Postfix) with ESMTPSA id 1138865D8E; Sat, 3 Mar 2012 21:21:17 +0100 (CET) Received: by fecusia (sSMTP sendmail emulation); Sat, 3 Mar 2012 21:21:16 +0100 From: "Linus Walleij" To: u-boot@lists.denx.de, Albert ARIBAUD Cc: Wolfgang Denk , Linus Walleij Subject: [PATCH] integrator: remove fragile delay loop from PCI code Date: Sat, 3 Mar 2012 21:21:13 +0100 Message-Id: <1330806073-32317-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.7.7.6 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlgQb/FQjuToJYg6AvMMkwg61ITROHXzs+O29EsBinRbahDs28qiQZdQ9UGH3/XYLyF/H3C The reference implementation of the PCI initialization code almost everywhere contain this fragile loop of "a few usecs", and its use of volatile variables to delay a number of bus cycles is indeed uncertain. Reading the manual "Integrator/AP Users Guide", page 5-15 it is clearly stated: "Wait until 230ms after the end of the reset period before accessing V360EPC internal registers. The V360EPC supports the use of a serial configuration PROM and the software must wait for the device to detect the absence of this PROM before accessing any registers. The required delay is a function of the PCI Clock, but at the lower frequency (25MHz) is 230ms". So let's simply wait 230ms per the spec. This solves the compilation error that looked like this: pci.c: In function ‘pci_init_board’: pci.c:286:18: warning: variable ‘j’ set but not used Reported-by: Wolfgang Denk Signed-off-by: Linus Walleij --- board/armltd/integrator/pci.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c index f040450..8ff88fe 100644 --- a/board/armltd/integrator/pci.c +++ b/board/armltd/integrator/pci.c @@ -283,17 +283,14 @@ struct pci_controller integrator_hose = { void pci_init_board(void) { - volatile int i, j; struct pci_controller *hose = &integrator_hose; u16 val; /* setting this register will take the V3 out of reset */ __raw_writel(SC_PCI_PCIEN, SC_PCI); - /* wait a few usecs to settle the device and the PCI bus */ - - for (i = 0; i < 100; i++) - j = i + 1; + /* Wait for 230 ms (from spec) before accessing any V3 registers */ + mdelay(230); /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));