From patchwork Fri Mar 2 13:25:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 7062 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CC31C1D0E53 for ; Fri, 2 Mar 2012 13:25:52 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 74F04A18500 for ; Fri, 2 Mar 2012 13:25:52 +0000 (UTC) Received: by iage36 with SMTP id e36so3079579iag.11 for ; Fri, 02 Mar 2012 05:25:51 -0800 (PST) Received: from mr.google.com ([10.50.170.41]) by 10.50.170.41 with SMTP id aj9mr1775056igc.0.1330694751990 (num_hops = 1); Fri, 02 Mar 2012 05:25:51 -0800 (PST) Received: by 10.50.170.41 with SMTP id aj9mr1471233igc.0.1330694751929; Fri, 02 Mar 2012 05:25:51 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp9391ibg; Fri, 2 Mar 2012 05:25:51 -0800 (PST) Received: by 10.68.201.135 with SMTP id ka7mr13299463pbc.145.1330694750805; Fri, 02 Mar 2012 05:25:50 -0800 (PST) Received: from mail-pw0-f50.google.com (mail-pw0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id 9si3696238pbr.228.2012.03.02.05.25.49 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 02 Mar 2012 05:25:50 -0800 (PST) Received-SPF: neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.50 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by pbcwz7 with SMTP id wz7so2364677pbc.37 for ; Fri, 02 Mar 2012 05:25:49 -0800 (PST) Received-SPF: pass (google.com: domain of chander.kashyap@linaro.org designates 10.68.238.136 as permitted sender) client-ip=10.68.238.136; Received: from mr.google.com ([10.68.238.136]) by 10.68.238.136 with SMTP id vk8mr16308712pbc.143.1330694749973 (num_hops = 1); Fri, 02 Mar 2012 05:25:49 -0800 (PST) MIME-Version: 1.0 Received: by 10.68.238.136 with SMTP id vk8mr13612630pbc.143.1330694749905; Fri, 02 Mar 2012 05:25:49 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f8sm5020696pbe.42.2012.03.02.05.25.44 (version=SSLv3 cipher=OTHER); Fri, 02 Mar 2012 05:25:48 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH] EXYNOS: Add structure for Exynos4 DMC Date: Fri, 2 Mar 2012 18:55:34 +0530 Message-Id: <1330694734-2956-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 X-Gm-Message-State: ALoCoQk8uCmu6r7+3rTlZskgbGgQ3rc2/LfJq0EvXsSSFBosjPWjnJWGZj5pWABhB5y3o6TcC3lO Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC). Signed-off-by: Chander Kashyap --- arch/arm/include/asm/arch-exynos/dmc.h | 109 ++++++++++++++++++++++++++++++++ 1 files changed, 109 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index debbe50..bd52d16 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -2,6 +2,115 @@ #define __DMC_H__ #ifndef __ASSEMBLY__ +struct exynos4_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int memconfig0; + unsigned int memconfig1; + unsigned int directcmd; + unsigned int prechconfig; + unsigned int phycontrol0; + unsigned int phycontrol1; + unsigned int phycontrol2; + unsigned int phycontrol3; + unsigned int pwrdnconfig; + unsigned char res1[0x4]; + unsigned int timingref; + unsigned int timingrow; + unsigned int timingdata; + unsigned int timingpower; + unsigned int phystatus; + unsigned int phyzqcontrol; + unsigned int chip0status; + unsigned int chip1status; + unsigned int arefstatus; + unsigned int mrstatus; + unsigned int phytest0; + unsigned int phytest1; + unsigned int qoscontrol0; + unsigned int qosconfig0; + unsigned int qoscontrol1; + unsigned int qosconfig1; + unsigned int qoscontrol2; + unsigned int qosconfig2; + unsigned int qoscontrol3; + unsigned int qosconfig3; + unsigned int qoscontrol4; + unsigned int qosconfig4; + unsigned int qoscontrol5; + unsigned int qosconfig5; + unsigned int qoscontrol6; + unsigned int qosconfig6; + unsigned int qoscontrol7; + unsigned int qosconfig7; + unsigned int qoscontrol8; + unsigned int qosconfig8; + unsigned int qoscontrol9; + unsigned int qosconfig9; + unsigned int qoscontrol10; + unsigned int qosconfig10; + unsigned int qoscontrol11; + unsigned int qosconfig11; + unsigned int qoscontrol12; + unsigned int qosconfig12; + unsigned int qoscontrol13; + unsigned int qosconfig13; + unsigned int qoscontrol14; + unsigned int qosconfig14; + unsigned int qoscontrol15; + unsigned int qosconfig15; + unsigned int qostimeout0; + unsigned int qostimeout1; + unsigned char res2[0x8]; + unsigned int ivcontrol; + unsigned char res3[0x8]; + unsigned int perevconfig; + unsigned char res4[0xDF00]; + unsigned int pmnc_ppc_a; + unsigned char res5[0xC]; + unsigned int cntens_ppc_a; + unsigned char res6[0xC]; + unsigned int cntenc_ppc_a; + unsigned char res7[0xC]; + unsigned int intens_ppc_a; + unsigned char res8[0xC]; + unsigned int intenc_ppc_a; + unsigned char res9[0xC]; + unsigned int flag_ppc_a; + unsigned char res10[0xAC]; + unsigned int ccnt_ppc_a; + unsigned char res11[0xC]; + unsigned int pmcnt0_ppc_a; + unsigned char res12[0xC]; + unsigned int pmcnt1_ppc_a; + unsigned char res13[0xC]; + unsigned int pmcnt2_ppc_a; + unsigned char res14[0xC]; + unsigned int pmcnt3_ppc_a; + unsigned char res15[0xEBC]; + unsigned int pmnc_ppc_m; + unsigned char res16[0xC]; + unsigned int cntens_ppc_m; + unsigned char res17[0xC]; + unsigned int cntenc_ppc_m; + unsigned char res18[0xC]; + unsigned int intens_ppc_m; + unsigned char res19[0xC]; + unsigned int intenc_ppc_m; + unsigned char res20[0xC]; + unsigned int flag_ppc_m; + unsigned char res21[0xAC]; + unsigned int ccnt_ppc_m; + unsigned char res22[0xC]; + unsigned int pmcnt0_ppc_m; + unsigned char res23[0xC]; + unsigned int pmcnt1_ppc_m; + unsigned char res24[0xC]; + unsigned int pmcnt2_ppc_m; + unsigned char res25[0xC]; + unsigned int pmcnt3_ppc_m; +}; + struct exynos5_dmc { unsigned int concontrol; unsigned int memcontrol;