From patchwork Mon Feb 6 09:01:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 6660 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0842623ECA for ; Mon, 6 Feb 2012 09:06:03 +0000 (UTC) Received: from mail-gx0-f180.google.com (mail-gx0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id CCB43A18198 for ; Mon, 6 Feb 2012 09:06:02 +0000 (UTC) Received: by ggnr1 with SMTP id r1so3367946ggn.11 for ; Mon, 06 Feb 2012 01:06:02 -0800 (PST) Received: by 10.50.15.231 with SMTP id a7mr19699744igd.8.1328519162194; Mon, 06 Feb 2012 01:06:02 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.169.210 with SMTP id a18cs84713ibz; Mon, 6 Feb 2012 01:06:01 -0800 (PST) Received: by 10.50.155.193 with SMTP id vy1mr19953560igb.14.1328519161417; Mon, 06 Feb 2012 01:06:01 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id k8si9065942icx.90.2012.02.06.01.06.00 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 06 Feb 2012 01:06:01 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by mail-iy0-f178.google.com with SMTP id e36so5728863iag.37 for ; Mon, 06 Feb 2012 01:06:00 -0800 (PST) Received: by 10.42.157.133 with SMTP id d5mr15825800icx.46.1328519160579; Mon, 06 Feb 2012 01:06:00 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id or2sm14805260igc.5.2012.02.06.01.05.56 (version=SSLv3 cipher=OTHER); Mon, 06 Feb 2012 01:05:59 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH v9 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro Date: Mon, 6 Feb 2012 14:31:45 +0530 Message-Id: <1328518908-2020-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328518908-2020-1-git-send-email-chander.kashyap@linaro.org> References: <1328518908-2020-1-git-send-email-chander.kashyap@linaro.org> CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap --- Changes for v2: - None Changes for v3: - None Changes for V4: - Added CONFIG_SYS_CLK_FREQ to trats.h Changes for v5: - None Changes for v6: - None Changes for v7: - None Changes for v8: - None Changes for v9: - None arch/arm/cpu/armv7/exynos/clock.c | 6 +----- include/configs/s5pc210_universal.h | 1 + include/configs/trats.h | 1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0c199cd..4d92c53 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_SYS_CLK_FREQ_C210 -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#endif - /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ_C210; + freq = CONFIG_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index be000cb..8286680 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -49,6 +49,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/trats.h b/include/configs/trats.h index acb3241..10f11d9 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -49,6 +49,7 @@ /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG