From patchwork Fri Feb 3 16:05:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 6595 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C58B623ECC for ; Fri, 3 Feb 2012 16:06:22 +0000 (UTC) Received: from mail-gx0-f180.google.com (mail-gx0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8DBADA1803F for ; Fri, 3 Feb 2012 16:06:22 +0000 (UTC) Received: by ggnr1 with SMTP id r1so2509407ggn.11 for ; Fri, 03 Feb 2012 08:06:22 -0800 (PST) Received: by 10.50.10.225 with SMTP id l1mr9236671igb.9.1328285181836; Fri, 03 Feb 2012 08:06:21 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.169.210 with SMTP id a18cs20858ibz; Fri, 3 Feb 2012 08:06:21 -0800 (PST) Received: by 10.236.80.4 with SMTP id j4mr12053971yhe.120.1328285180863; Fri, 03 Feb 2012 08:06:20 -0800 (PST) Received: from mail-gy0-f178.google.com (mail-gy0-f178.google.com [209.85.160.178]) by mx.google.com with ESMTPS id n61si6964787yhk.93.2012.02.03.08.06.20 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Feb 2012 08:06:20 -0800 (PST) Received-SPF: neutral (google.com: 209.85.160.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.160.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by ghbf14 with SMTP id f14so2065467ghb.37 for ; Fri, 03 Feb 2012 08:06:20 -0800 (PST) Received: by 10.50.140.105 with SMTP id rf9mr13926734igb.24.1328285180410; Fri, 03 Feb 2012 08:06:20 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id g34sm11915981ibk.10.2012.02.03.08.06.16 (version=SSLv3 cipher=OTHER); Fri, 03 Feb 2012 08:06:19 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH v8 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro Date: Fri, 3 Feb 2012 21:35:54 +0530 Message-Id: <1328285157-23780-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328285157-23780-1-git-send-email-chander.kashyap@linaro.org> References: <1328285157-23780-1-git-send-email-chander.kashyap@linaro.org> CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap --- Changes for v2: - None Changes for v3: - None Changes for V4: - Added CONFIG_SYS_CLK_FREQ to trats.h Changes for v5: - None Changes for v6: - None Changes for v7: - None Changes for v8: - None arch/arm/cpu/armv7/exynos/clock.c | 6 +----- include/configs/s5pc210_universal.h | 1 + include/configs/trats.h | 1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0c199cd..4d92c53 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_SYS_CLK_FREQ_C210 -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#endif - /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ_C210; + freq = CONFIG_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index be000cb..8286680 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -49,6 +49,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/trats.h b/include/configs/trats.h index acb3241..10f11d9 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -49,6 +49,7 @@ /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG