From patchwork Thu Dec 22 10:52:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 5948 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C32F72401D for ; Thu, 22 Dec 2011 10:53:28 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id B2A3DA18506 for ; Thu, 22 Dec 2011 10:53:28 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id c11so5602457eaa.11 for ; Thu, 22 Dec 2011 02:53:28 -0800 (PST) Received: by 10.205.141.78 with SMTP id jd14mr2930536bkc.107.1324551208513; Thu, 22 Dec 2011 02:53:28 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs62445bkc; Thu, 22 Dec 2011 02:53:28 -0800 (PST) Received: by 10.50.77.227 with SMTP id v3mr8095991igw.8.1324551206017; Thu, 22 Dec 2011 02:53:26 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id io5si11395156igc.57.2011.12.22.02.53.25 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Dec 2011 02:53:26 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by mail-iy0-f178.google.com with SMTP id f6so16051681iag.37 for ; Thu, 22 Dec 2011 02:53:25 -0800 (PST) Received: by 10.50.170.35 with SMTP id aj3mr8293924igc.2.1324551205316; Thu, 22 Dec 2011 02:53:25 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f32sm24601659ibf.9.2011.12.22.02.53.21 (version=SSLv3 cipher=OTHER); Thu, 22 Dec 2011 02:53:24 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH 2/6] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro Date: Thu, 22 Dec 2011 16:22:44 +0530 Message-Id: <1324551168-1202-3-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1324551168-1202-1-git-send-email-chander.kashyap@linaro.org> References: <1324551168-1202-1-git-send-email-chander.kashyap@linaro.org> CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (EXYNOS4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap --- arch/arm/cpu/armv7/exynos/clock.c | 6 +----- include/configs/s5pc210_universal.h | 1 + 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0c199cd..4d92c53 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_SYS_CLK_FREQ_C210 -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#endif - /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ_C210; + freq = CONFIG_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 33c4600..18de956 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -50,6 +50,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG