From patchwork Mon Dec 19 08:56:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 5867 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E8AAA24056 for ; Mon, 19 Dec 2011 08:57:21 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id D1507A183CF for ; Mon, 19 Dec 2011 08:57:21 +0000 (UTC) Received: by mail-ey0-f180.google.com with SMTP id c11so1639295eaa.11 for ; Mon, 19 Dec 2011 00:57:21 -0800 (PST) Received: by 10.205.120.14 with SMTP id fw14mr1088669bkc.53.1324285041679; Mon, 19 Dec 2011 00:57:21 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.82.144 with SMTP id ac16cs946bkc; Mon, 19 Dec 2011 00:57:21 -0800 (PST) Received: by 10.50.77.194 with SMTP id u2mr27547266igw.2.1324285039378; Mon, 19 Dec 2011 00:57:19 -0800 (PST) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id ad3si5709048igc.20.2011.12.19.00.57.18 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 19 Dec 2011 00:57:19 -0800 (PST) Received-SPF: neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by mail-iy0-f178.google.com with SMTP id f6so10003704iag.37 for ; Mon, 19 Dec 2011 00:57:18 -0800 (PST) Received: by 10.50.156.129 with SMTP id we1mr27699149igb.60.1324285038643; Mon, 19 Dec 2011 00:57:18 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id rc7sm18763346igb.0.2011.12.19.00.57.15 (version=SSLv3 cipher=OTHER); Mon, 19 Dec 2011 00:57:18 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH V2 2/2] Exynos: Fix ARM Clock frequency calculation Date: Mon, 19 Dec 2011 14:26:44 +0530 Message-Id: <1324285004-32354-3-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1324285004-32354-1-git-send-email-chander.kashyap@linaro.org> References: <1324285004-32354-1-git-send-email-chander.kashyap@linaro.org> Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap --- Changes for V2: - Fixed commit comment - Fixed comment in clock.c "exynos4_get_arm_clk ()" - Renamed dout_apll to armclk in clock.c "exynos4_get_arm_clk ()" arch/arm/cpu/armv7/exynos/clock.c | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 64de262..0c199cd 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -102,17 +102,20 @@ static unsigned long exynos4_get_arm_clk(void) struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); unsigned long div; - unsigned long dout_apll; - unsigned int apll_ratio; + unsigned long armclk; + unsigned int core_ratio; + unsigned int core2_ratio; div = readl(&clk->div_cpu0); - /* APLL_RATIO: [26:24] */ - apll_ratio = (div >> 24) & 0x7; + /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ + core_ratio = (div >> 0) & 0x7; + core2_ratio = (div >> 28) & 0x7; - dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); + armclk = get_pll_clk(APLL) / (core_ratio + 1); + armclk /= (core2_ratio + 1); - return dout_apll; + return armclk; } /* exynos4: return pwm clock frequency */