From patchwork Wed Nov 9 16:16:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4980 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9DB2B23E0C for ; Wed, 9 Nov 2011 16:16:43 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 8A41CA1888A for ; Wed, 9 Nov 2011 16:16:43 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id c12so2251965bkb.11 for ; Wed, 09 Nov 2011 08:16:43 -0800 (PST) Received: by 10.152.144.202 with SMTP id so10mr2029451lab.9.1320855403287; Wed, 09 Nov 2011 08:16:43 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.10.72 with SMTP id g8cs176249lab; Wed, 9 Nov 2011 08:16:43 -0800 (PST) Received: by 10.204.141.65 with SMTP id l1mr2231136bku.82.1320855401792; Wed, 09 Nov 2011 08:16:41 -0800 (PST) Received: from mail.df.lth.se (mail.df.lth.se. [194.47.250.12]) by mx.google.com with ESMTPS id zy3si3105163bkb.96.2011.11.09.08.16.41 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 Nov 2011 08:16:41 -0800 (PST) Received-SPF: neutral (google.com: 194.47.250.12 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=194.47.250.12; Authentication-Results: mx.google.com; spf=neutral (google.com: 194.47.250.12 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) smtp.mail=linus.walleij@linaro.org Received: from Fecusia (c83-249-208-177.bredband.comhem.se [83.249.208.177]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.df.lth.se (Postfix) with ESMTPSA id CDF3A65D7A; Wed, 9 Nov 2011 17:16:40 +0100 (CET) Received: by Fecusia (sSMTP sendmail emulation); Wed, 9 Nov 2011 17:16:39 +0100 From: Linus Walleij To: Albert ARIBAUD Cc: u-boot@lists.denx.de, Linus Walleij Subject: [PATCH 7/7 v3] integrator: enable Vpp and disable flash protection Date: Wed, 9 Nov 2011 17:16:37 +0100 Message-Id: <1320855397-4296-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.7.6.4 This enables Vpp and disables the flash protection on the Integrator when starting U-Boot. The integrator/AP has double protection mechanisms: this one and the EBI protection bit (patch earlier), the Integrator/CP has only one line of protection in these registers. Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Rebased to U-Boot ARM HEAD at Alberts request, see message 4EA1C8E7.7090105@aribaud.net ChangeLog v2->v3: - Rebased to U-Boot ARM HEAD at Alberts request, see message 4EB84700.1030109@aribaud.net --- board/armltd/integrator/integrator.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index dd83ca5..a507c09 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -37,6 +37,7 @@ #include #include #include "arm-ebi.h" +#include "integrator-sc.h" DECLARE_GLOBAL_DATA_PTR; @@ -76,7 +77,19 @@ extern void cm_remap(void); cm_remap(); /* remaps writeable memory to 0x00000000 */ #endif +#ifdef CONFIG_ARCH_CINTEGRATOR /* + * Flash protection on the Integrator/CP is in a simple register + */ + val = readl(CP_FLASHPROG); + val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN); + writel(val, CP_FLASHPROG); +#else + /* + * The Integrator/AP has some special protection mechanisms + * for the external memories, first the External Bus Interface (EBI) + * then the system controller (SC). + * * The system comes up with the flash memory non-writable and * configuration locked. If we want U-Boot to be used for flash * access we cannot have the flash memory locked. @@ -88,6 +101,13 @@ extern void cm_remap(void); writel(val, EBI_BASE + EBI_CSR1_REG); writel(0, EBI_BASE + EBI_LOCK_REG); + /* + * Set up the system controller to remove write protection from + * the flash memory and enable Vpp + */ + writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); +#endif + icache_enable (); return 0;