From patchwork Wed Sep 21 20:17:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Salveti X-Patchwork-Id: 4231 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C951123EFD for ; Wed, 21 Sep 2011 20:18:15 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id BED7CA18656 for ; Wed, 21 Sep 2011 20:18:15 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id 23so2878814fxe.11 for ; Wed, 21 Sep 2011 13:18:15 -0700 (PDT) Received: by 10.223.63.8 with SMTP id z8mr1623256fah.84.1316636295658; Wed, 21 Sep 2011 13:18:15 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.18.198 with SMTP id y6cs142608lad; Wed, 21 Sep 2011 13:18:15 -0700 (PDT) Received: by 10.100.13.16 with SMTP id 16mr1207694anm.110.1316636294604; Wed, 21 Sep 2011 13:18:14 -0700 (PDT) Received: from mail-gw0-f49.google.com (mail-gw0-f49.google.com [74.125.83.49]) by mx.google.com with ESMTPS id 10si4391065anm.161.2011.09.21.13.18.13 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 21 Sep 2011 13:18:14 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.83.49 is neither permitted nor denied by best guess record for domain of ricardo.salveti@linaro.org) client-ip=74.125.83.49; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.83.49 is neither permitted nor denied by best guess record for domain of ricardo.salveti@linaro.org) smtp.mail=ricardo.salveti@linaro.org Received: by gwa2 with SMTP id 2so636851gwa.36 for ; Wed, 21 Sep 2011 13:18:13 -0700 (PDT) Received: by 10.101.165.30 with SMTP id s30mr1194734ano.57.1316636293006; Wed, 21 Sep 2011 13:18:13 -0700 (PDT) Received: from localhost.localdomain ([189.61.233.110]) by mx.google.com with ESMTPS id h20sm24134769ann.7.2011.09.21.13.18.10 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 21 Sep 2011 13:18:12 -0700 (PDT) From: Ricardo Salveti de Araujo To: u-boot@lists.denx.de Cc: patches@linaro.org, aneesh@ti.com, john.rigby@linaro.org, s-jan@ti.com, s-paulraj@ti.com, Ricardo Salveti de Araujo Subject: [PATCH 2/3] omap4: adding revision detection for 4460 ES1.1 Date: Wed, 21 Sep 2011 17:17:30 -0300 Message-Id: <1316636251-23961-3-git-send-email-ricardo.salveti@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1316636251-23961-1-git-send-email-ricardo.salveti@linaro.org> References: <1316636251-23961-1-git-send-email-ricardo.salveti@linaro.org> Signed-off-by: Ricardo Salveti de Araujo 2 files changed, 17 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 140562b..d9639ab 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -218,7 +218,17 @@ static void init_omap4_revision(void) *omap4_revision = OMAP4430_ES2_3; break; case MIDR_CORTEX_A9_R2P10: - *omap4_revision = OMAP4460_ES1_0; + switch (readl(CONTROL_ID_CODE)) { + case OMAP4460_CONTROL_ID_CODE_ES1_0: + *omap4_revision = OMAP4460_ES1_0; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_1: + *omap4_revision = OMAP4460_ES1_1; + break; + default: + *omap4_revision = OMAP4460_ES1_0; + break; + } break; default: *omap4_revision = OMAP4430_SILICON_ID_INVALID; diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 5d2d01d..162ab43 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -57,12 +57,17 @@ /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 +/* 4430 */ #define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F #define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F #define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F #define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F #define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F +/* 4460 */ +#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F +#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F + /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) @@ -185,6 +190,7 @@ struct control_lpddr2io_regs { #define OMAP4430_ES2_2 0x44300220 #define OMAP4430_ES2_3 0x44300230 #define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 /* ROM code defines */ /* Boot device */