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RISC-V SiFive FU540 support SPL
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| 4 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v8,19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
RISC-V SiFive FU540 support SPL
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2020-05-09
Pragnesh Patel
New
[v8,14/21] riscv: Add place-holder for driver compilation
RISC-V SiFive FU540 support SPL
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-
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2020-05-09
Pragnesh Patel
New
[v8,13/21] riscv: cpu: fu540: Add support for cpu fu540
RISC-V SiFive FU540 support SPL
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-
-
2020-05-09
Pragnesh Patel
New
[v8,11/21] clk: sifive: fu540-prci: Add ehternet clock initialization in SPL
RISC-V SiFive FU540 support SPL
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2020-05-09
Pragnesh Patel
New