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Mon, 25 Nov 2024 00:34:29 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825f98b3a4sm10013421f8f.0.2024.11.25.00.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2024 00:34:29 -0800 (PST) From: Neil Armstrong Subject: [PATCH 0/4] clk: qcom: add PCIe clocks Date: Mon, 25 Nov 2024 09:34:25 +0100 Message-Id: <20241125-topic-pcie-clk-v1-0-4315d1e4e164@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAJE2RGcC/x3MQQqAIBBA0avErBtIK4quEi1knGooVDQiCO+et HyL/19IHIUTTNULkW9J4l2Bqiug3biNUWwx6EZ3SukeLx+EMJAw0nngyG3X29EQDwZKFCKv8vz Decn5AxfNIfJgAAAA X-Change-ID: 20241125-topic-pcie-clk-8e345d8ace7a To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Sumit Garg , Tom Rini Cc: u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1053; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=jYNgRXjvGSiarvMG7dlJyGEvg61/N2e52gONoI1JQdo=; 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Depends on: - https://lore.kernel.org/all/20241118-topic-x1e80100-clk-v1-0-8841e87ad81f@linaro.org/ Signed-off-by: Neil Armstrong --- Neil Armstrong (4): clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock clk: qcom: sm8550: add support for PCIe clocks clk: qcom: sm8650: add support for PCIe clocks clk: qcom: x1e80100: add support for PCIe clocks drivers/clk/qcom/clock-qcom.c | 19 ++++++++++++++ drivers/clk/qcom/clock-qcom.h | 2 ++ drivers/clk/qcom/clock-sm8550.c | 36 ++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm8650.c | 36 ++++++++++++++++++++++++++ drivers/clk/qcom/clock-x1e80100.c | 54 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 147 insertions(+) --- base-commit: c7934881aa75d34aea2493322de0a417524ebf4a change-id: 20241125-topic-pcie-clk-8e345d8ace7a Best regards,