| Message ID | 20240819-b4-qcom-clk-dump-v1-0-182cf77c23a2@linaro.org |
|---|---|
| Headers | show |
| Series | clk/qcom: implement clk dump callback | expand |
Hi Lukasz, Could you take a quick look at this? Thanks and kind regards, On 19/08/2024 21:34, Caleb Connolly wrote: > Add support for dumping a few of the clocks used on Qualcomm platforms. > Naming the Global PLL's, Root Clock Generators, and gate clocks. > > This helps a lot with platform bringup and feature enablement by making > it easy to sanity check that the clocks are programmed correctly. > > == Usage == > > Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of > qcom-<soc>.c. > > If your SoC doesn't yet define the debug data for clocks, it can be > added using the Linux driver as a reference. > > The "clk dump" command should print the states of all the gates, GPLLs > and RCGs for your SoC. > > == Glossary == > > RCG: Root Clock Generator > * Takes in some fairly arbitrary high freq clock (configurable clock > source and options for taking just even pulses and other things) > * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary > 8 or 16-bit values (depending on the RCG), and d is a number (with > support for .5 offsets). > > GPLL: Global Phase Locked Loop > * Crystal as input > * integer multiplier + exponent part (2^-40) > > Gate: Simple on/off clock > * Put between RCGs and the peripherals they power > * Required to allow for correct power sequencing > > If you do the maths manually using the equations from "clk dump", the > numbers should roughly line up by they're likely to be out by a handful > of MHz. They output is formatted so that it can be pasted directly into > the python interpreter. > > == Example output == > > => clk dump > Rate Usecnt Name > ------------------------------------------ > 38400000 0 |-- xo-board > 32764 0 |-- sleep-clk > > qcom_clk qcom_clk: > Gate Clocks: > GCC_AGGRE_USB3_SEC_AXI_CLK : > GCC_CFG_NOC_USB3_SEC_AXI_CLK : > GCC_QUPV3_WRAP0_S0_CLK : > GCC_QUPV3_WRAP0_S1_CLK : > GCC_QUPV3_WRAP0_S2_CLK : > GCC_QUPV3_WRAP0_S3_CLK : > GCC_QUPV3_WRAP0_S4_CLK : > GCC_QUPV3_WRAP0_S5_CLK : > GCC_QUPV3_WRAP0_S6_CLK : > GCC_QUPV3_WRAP0_S7_CLK : > GCC_QUPV3_WRAP1_S0_CLK : > GCC_QUPV3_WRAP1_S1_CLK : ON > GCC_QUPV3_WRAP1_S3_CLK : > GCC_QUPV3_WRAP1_S4_CLK : > GCC_QUPV3_WRAP1_S5_CLK : > GCC_QUPV3_WRAP1_S6_CLK : > GCC_QUPV3_WRAP1_S7_CLK : > GCC_QUPV3_WRAP_0_M_AHB_CLK : > GCC_QUPV3_WRAP_0_S_AHB_CLK : > GCC_QUPV3_WRAP_1_M_AHB_CLK : ON > GCC_QUPV3_WRAP_1_S_AHB_CLK : ON > GCC_SDCC2_AHB_CLK : ON > GCC_SDCC2_APPS_CLK : ON > GCC_SDCC4_AHB_CLK : > GCC_SDCC4_APPS_CLK : > GCC_UFS_CARD_AHB_CLK : > GCC_UFS_CARD_AXI_CLK : > GCC_UFS_CARD_CLKREF_CLK : ON > GCC_UFS_CARD_ICE_CORE_CLK : > GCC_UFS_CARD_PHY_AUX_CLK : > GCC_UFS_CARD_RX_SYMBOL_0_CLK : > GCC_UFS_CARD_RX_SYMBOL_1_CLK : > GCC_UFS_CARD_TX_SYMBOL_0_CLK : > GCC_UFS_CARD_UNIPRO_CORE_CLK : > GCC_UFS_MEM_CLKREF_CLK : ON > GCC_UFS_PHY_AHB_CLK : ON > GCC_UFS_PHY_AXI_CLK : ON > GCC_UFS_PHY_ICE_CORE_CLK : ON > GCC_UFS_PHY_PHY_AUX_CLK : ON > GCC_UFS_PHY_RX_SYMBOL_0_CLK : ON > GCC_UFS_PHY_RX_SYMBOL_1_CLK : ON > GCC_UFS_PHY_TX_SYMBOL_0_CLK : ON > GCC_UFS_PHY_UNIPRO_CORE_CLK : ON > GCC_USB30_PRIM_MASTER_CLK : ON > GCC_USB30_PRIM_MOCK_UTMI_CLK : ON > GCC_USB30_PRIM_SLEEP_CLK : ON > GCC_USB30_SEC_MASTER_CLK : > GCC_USB30_SEC_MOCK_UTMI_CLK : > GCC_USB30_SEC_SLEEP_CLK : > GCC_USB3_PRIM_CLKREF_CLK : ON > GCC_USB3_PRIM_PHY_AUX_CLK : ON > GCC_USB3_PRIM_PHY_COM_AUX_CLK : ON > GCC_USB3_PRIM_PHY_PIPE_CLK : ON > GCC_USB3_SEC_CLKREF_CLK : ON > GCC_USB3_SEC_PHY_AUX_CLK : > GCC_USB3_SEC_PHY_PIPE_CLK : > GCC_USB3_SEC_PHY_COM_AUX_CLK : > GCC_USB_PHY_CFG_AHB2PHY_CLK : ON > > GPLL clocks: > | GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA | > +--------+--------+-----------+------------+----------------+ > | GPLL0 | X | 19200000 * (0x1f + 0x0 * 2 ** -40 )/ 1000000 > | GPLL1 | X | 19200000 * (0x37 + 0x0 * 2 ** -40 ) / 1000000 > | GPLL2 | | 19200000 * (0x14 + 0x0 * 2 ** -40 ) / 1000000 > | GPLL3 | | 19200000 * (0x30 + 0x0 * 2 ** -40 )/ 1000000 > | GPLL4 | X | 19200000 * (0x29 + 0x0 * 2 ** -40 ) / 1000000 > | GPLL5 | | 19200000 * (0x30 + 0x0 * 2 ** -40 ) / 1000000 > | GPLL6 | | 19200000 * (0x0 + 0x0 * 2 ** -40 )/ 1000000 > > RCGs: > | NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] | > +----------------------------------+----+-----+---------------------------------------+--------------+ > GCC_USB30_PRIM_MASTER | X | 1 | input_freq * ( 1/ 1) * (1/4.5) | [0x00000000] > GCC_USB30_PRIM_MOCK_UTMI | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] > GCC_USB3_PRIM_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] > GCC_USB30_SEC_MASTER | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_USB30_SEC_MOCK_UTMI | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_USB3_SEC_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_SDCC2_APPS | X | 5 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] > GCC_SDCC4_APPS | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_CORE_2X | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] > GCC_QUPV3_WRAP0_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S1 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S2 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP0_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP1_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP1_S1 | X | 6 | input_freq * ( 384/15625) * (1/1 ) | [0x00000000] > GCC_QUPV3_WRAP1_S2 | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] > GCC_QUPV3_WRAP1_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP1_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP1_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP1_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_QUPV3_WRAP1_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_PCIE_0_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_PCIE_1_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_PCIE_PHY_REFGEN | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] > GCC_UFS_CARD_AXI | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] > GCC_UFS_CARD_ICE_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_UFS_CARD_UNIPRO_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_UFS_CARD_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] > GCC_UFS_PHY_AXI | X | 1 | input_freq * ( 1/ 1) * (1/3 ) | [0x00000000] > GCC_UFS_PHY_ICE_CORE | X | 1 | input_freq * ( 1/ 1) * (1/2 ) | [0x00000000] > GCC_UFS_PHY_UNIPRO_CORE | X | 1 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] > GCC_UFS_PHY_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] > > --- > Caleb Connolly (4): > clk/qcom: implement clk dump > clk/qcom: sdm845: add dump data > clk/qcom: sm6115: add debug data > clk/qcom: sm8250: add debug data > > drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/clock-qcom.h | 6 +++ > drivers/clk/qcom/clock-sdm845.c | 93 ++++++++++++++++++++++++++++++++ > drivers/clk/qcom/clock-sm6115.c | 63 ++++++++++++++++++++++ > drivers/clk/qcom/clock-sm8250.c | 115 +++++++++++++++++++++++++++++++++++++++ > 5 files changed, 394 insertions(+) > --- > change-id: 20240819-b4-qcom-clk-dump-e25a0198f6c0 > base-commit: b7d5ce05b1b52136af09cf34541c6a91079a4b86 > > // Caleb (they/them) >
Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c. If your SoC doesn't yet define the debug data for clocks, it can be added using the Linux driver as a reference. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. == Example output == => clk dump Rate Usecnt Name ------------------------------------------ 38400000 0 |-- xo-board 32764 0 |-- sleep-clk qcom_clk qcom_clk: Gate Clocks: GCC_AGGRE_USB3_SEC_AXI_CLK : GCC_CFG_NOC_USB3_SEC_AXI_CLK : GCC_QUPV3_WRAP0_S0_CLK : GCC_QUPV3_WRAP0_S1_CLK : GCC_QUPV3_WRAP0_S2_CLK : GCC_QUPV3_WRAP0_S3_CLK : GCC_QUPV3_WRAP0_S4_CLK : GCC_QUPV3_WRAP0_S5_CLK : GCC_QUPV3_WRAP0_S6_CLK : GCC_QUPV3_WRAP0_S7_CLK : GCC_QUPV3_WRAP1_S0_CLK : GCC_QUPV3_WRAP1_S1_CLK : ON GCC_QUPV3_WRAP1_S3_CLK : GCC_QUPV3_WRAP1_S4_CLK : GCC_QUPV3_WRAP1_S5_CLK : GCC_QUPV3_WRAP1_S6_CLK : GCC_QUPV3_WRAP1_S7_CLK : GCC_QUPV3_WRAP_0_M_AHB_CLK : GCC_QUPV3_WRAP_0_S_AHB_CLK : GCC_QUPV3_WRAP_1_M_AHB_CLK : ON GCC_QUPV3_WRAP_1_S_AHB_CLK : ON GCC_SDCC2_AHB_CLK : ON GCC_SDCC2_APPS_CLK : ON GCC_SDCC4_AHB_CLK : GCC_SDCC4_APPS_CLK : GCC_UFS_CARD_AHB_CLK : GCC_UFS_CARD_AXI_CLK : GCC_UFS_CARD_CLKREF_CLK : ON GCC_UFS_CARD_ICE_CORE_CLK : GCC_UFS_CARD_PHY_AUX_CLK : GCC_UFS_CARD_RX_SYMBOL_0_CLK : GCC_UFS_CARD_RX_SYMBOL_1_CLK : GCC_UFS_CARD_TX_SYMBOL_0_CLK : GCC_UFS_CARD_UNIPRO_CORE_CLK : GCC_UFS_MEM_CLKREF_CLK : ON GCC_UFS_PHY_AHB_CLK : ON GCC_UFS_PHY_AXI_CLK : ON GCC_UFS_PHY_ICE_CORE_CLK : ON GCC_UFS_PHY_PHY_AUX_CLK : ON GCC_UFS_PHY_RX_SYMBOL_0_CLK : ON GCC_UFS_PHY_RX_SYMBOL_1_CLK : ON GCC_UFS_PHY_TX_SYMBOL_0_CLK : ON GCC_UFS_PHY_UNIPRO_CORE_CLK : ON GCC_USB30_PRIM_MASTER_CLK : ON GCC_USB30_PRIM_MOCK_UTMI_CLK : ON GCC_USB30_PRIM_SLEEP_CLK : ON GCC_USB30_SEC_MASTER_CLK : GCC_USB30_SEC_MOCK_UTMI_CLK : GCC_USB30_SEC_SLEEP_CLK : GCC_USB3_PRIM_CLKREF_CLK : ON GCC_USB3_PRIM_PHY_AUX_CLK : ON GCC_USB3_PRIM_PHY_COM_AUX_CLK : ON GCC_USB3_PRIM_PHY_PIPE_CLK : ON GCC_USB3_SEC_CLKREF_CLK : ON GCC_USB3_SEC_PHY_AUX_CLK : GCC_USB3_SEC_PHY_PIPE_CLK : GCC_USB3_SEC_PHY_COM_AUX_CLK : GCC_USB_PHY_CFG_AHB2PHY_CLK : ON GPLL clocks: | GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA | +--------+--------+-----------+------------+----------------+ | GPLL0 | X | 19200000 * (0x1f + 0x0 * 2 ** -40 )/ 1000000 | GPLL1 | X | 19200000 * (0x37 + 0x0 * 2 ** -40 ) / 1000000 | GPLL2 | | 19200000 * (0x14 + 0x0 * 2 ** -40 ) / 1000000 | GPLL3 | | 19200000 * (0x30 + 0x0 * 2 ** -40 )/ 1000000 | GPLL4 | X | 19200000 * (0x29 + 0x0 * 2 ** -40 ) / 1000000 | GPLL5 | | 19200000 * (0x30 + 0x0 * 2 ** -40 ) / 1000000 | GPLL6 | | 19200000 * (0x0 + 0x0 * 2 ** -40 )/ 1000000 RCGs: | NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] | +----------------------------------+----+-----+---------------------------------------+--------------+ GCC_USB30_PRIM_MASTER | X | 1 | input_freq * ( 1/ 1) * (1/4.5) | [0x00000000] GCC_USB30_PRIM_MOCK_UTMI | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB3_PRIM_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB30_SEC_MASTER | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB30_SEC_MOCK_UTMI | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB3_SEC_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_SDCC2_APPS | X | 5 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_SDCC4_APPS | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_CORE_2X | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_QUPV3_WRAP0_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S1 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S2 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S1 | X | 6 | input_freq * ( 384/15625) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S2 | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_0_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_1_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_PHY_REFGEN | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_AXI | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_ICE_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_UNIPRO_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_PHY_AXI | X | 1 | input_freq * ( 1/ 1) * (1/3 ) | [0x00000000] GCC_UFS_PHY_ICE_CORE | X | 1 | input_freq * ( 1/ 1) * (1/2 ) | [0x00000000] GCC_UFS_PHY_UNIPRO_CORE | X | 1 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_UFS_PHY_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] --- Caleb Connolly (4): clk/qcom: implement clk dump clk/qcom: sdm845: add dump data clk/qcom: sm6115: add debug data clk/qcom: sm8250: add debug data drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ drivers/clk/qcom/clock-sdm845.c | 93 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm6115.c | 63 ++++++++++++++++++++++ drivers/clk/qcom/clock-sm8250.c | 115 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+) --- change-id: 20240819-b4-qcom-clk-dump-e25a0198f6c0 base-commit: b7d5ce05b1b52136af09cf34541c6a91079a4b86 // Caleb (they/them)