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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id g13-20020a5d488d000000b00347321735a6sm7931517wrq.66.2024.04.15.05.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 05:44:31 -0700 (PDT) From: Caleb Connolly Subject: [PATCH 0/3] qcom: serial_msm: calculate UARTDM_CSR automatically Date: Mon, 15 Apr 2024 13:44:19 +0100 Message-Id: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIACMhHWYC/x3MywqAIBBA0V+JWTegor1+JVpoTTXQC5UIon/PW t7FuTcE8kwBmuwGTycH3rcUMs+gn+02EfKQGpRQWmhp0Glcw4ofsws6jt5GwrJwpjZSKFNWkOz haeTr/7bd87yRTOCNZwAAAA== To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Neil Armstrong , Sumit Garg , Tom Rini Cc: Robert Marko , u-boot-qcom@groups.io, u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1088; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=Pa4tfKvOR7b90zOF66gGxQC8pzyBM4Ez+75AQJEJWt4=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjRZRb3pyivcfHZ8CBVXn3BsV5C4gY1j8olzB6cxijTd0 do8/0F1RykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZhIlhHDP7UIDfO1eQ96Wh4p s09dMX3adHbnvbnmP31+zXg/o1s/7AHDf0cFp1PrNqxW0594OqufZ2+s4fY9PnKJS+a+euptyrl C8wAA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The msm serial UART controller has a bit clock divider register which much be programmed based on the UART clock. This changes per soc and currently is expected to be specified in DT or otherwise selected per board. This series fixes the apq8016 and ipq4019 clock drivers to return the programmed UART clock rate in clk_set_rate(), it then uses this clock rate and the hardcoded baud rate supported by this driver to calculate the correct value for the UARTDM_CSR register. --- Caleb Connolly (3): clk/qcom: apq8016: return valid rate when setting UART clock clk/qcom: ipq4019: return valid rate when setting UART clock serial: msm: calculate bit clock divider doc/device-tree-bindings/serial/msm-serial.txt | 10 --- drivers/clk/qcom/clock-apq8016.c | 4 +- drivers/clk/qcom/clock-ipq4019.c | 2 +- drivers/serial/serial_msm.c | 87 +++++++++++++++++++++----- 4 files changed, 73 insertions(+), 30 deletions(-) --- base-commit: 42f6978987336cff3d98d9cc4643c54a1eb0f36d // Caleb (they/them)