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([223.178.208.32]) by smtp.gmail.com with ESMTPSA id k2-20020aa788c2000000b006e13a88d52esm3392842pff.61.2024.02.26.00.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 00:05:11 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: marcel.ziswiler@toradex.com, francesco@dolcini.it, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, jh80.chung@samsung.com, festevam@denx.de, andrejs.cainikovs@toradex.com, sjg@chromium.org, peng.fan@nxp.com, aford173@gmail.com, marex@denx.de, ilias.apalodimas@linaro.org, sahaj.sarup@linaro.org, fathi.boudra@linaro.org, remi.duraffort@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 0/8] imx8mp: Enable PCIe/NVMe support Date: Mon, 26 Feb 2024 13:34:25 +0530 Message-Id: <20240226080433.3307154-1-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is rather tied to quite old port of pcie_designware driver from Linux which suffices only iMX6 specific needs. But currently we have the common DWC specific bits which alligns pretty well with DW PCIe controller on iMX8MP SoC. So lets reuse those common bits instead as a new driver for iMX8 SoCs. It should be fairly easy to add support for other iMX8 variants to this driver. iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we can reuse the generic PHY infrastructure to power on PCIe PHY. Patch #1: Adds PCIe clocks support. Patch #2: Adds i.MX8MP reset controller support. Patch #3: Extend i.MX8MP power domain driver with PCIe support Patch #4: Expose high performance PLL clock required for PCIe PHY on verdin board. Patch #5: Adds standalone PCIe PHY support for i.MX8MP SoC. Patch #6: Adds DW PCIe controller support for iMX8MP SoC. Patch #7: Enable PCIe/NVMe support for verdin board. Testing with this patch-set included: Verdin iMX8MP # pci enum PCIE-0: Link up (Gen1-x1, Bus0) Verdin iMX8MP # Verdin iMX8MP # nvme scan Verdin iMX8MP # Verdin iMX8MP # nvme info Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000000000000000720 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) Verdin iMX8MP # Verdin iMX8MP # load nvme 0 $loadaddr Changes in v2: - Renamed PCIe IMX driver pcie_dw_imx8.c -> pcie_dw_imx.c. - Added myself as maintainer for PCIe DWC IMX driver support. - Incorporated various code and commit message improvement suggestions from Marek, thanks. - Patch#3: Gate PCIe and USB clocks behind corresponding power domain IDs. - Patch#4: Expose HSIO PLL clocks as a regular clock driver instead similar to what Linux kernel does. - Patch#7: Picked up tags. Sumit Garg (8): clk: imx8mp: Add support for PCIe clocks reset: imx: Add support for i.MX8MP reset controller imx8mp: power-domain: Add PCIe support imx8mp: power-domain: Expose high performance PLL clock phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY pci: Add DW PCIe controller support for iMX8MP SoC verdin-imx8mp_defconfig: Enable PCIe/NVMe support MAINTAINERS: Add entry for PCIe DWC IMX driver MAINTAINERS | 6 + configs/verdin-imx8mp_defconfig | 6 + drivers/clk/imx/clk-imx8mp.c | 6 + drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_imx.c | 314 ++++++++++++++++++++++++++ drivers/phy/Kconfig | 9 + drivers/phy/Makefile | 1 + drivers/phy/phy-imx8m-pcie.c | 269 ++++++++++++++++++++++ drivers/power/domain/imx8mp-hsiomix.c | 179 +++++++++++++-- drivers/reset/reset-imx7.c | 114 ++++++++++ 11 files changed, 890 insertions(+), 23 deletions(-) create mode 100644 drivers/pci/pcie_dw_imx.c create mode 100644 drivers/phy/phy-imx8m-pcie.c